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| author | Clifford Wolf <clifford@clifford.at> | 2016-09-08 11:17:05 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-09-08 11:17:05 +0200 |
| commit | 2c0d818296eda10f763287784b749a712bfeda98 (patch) | |
| tree | e3409122df5c3b2c651ddcdc7ce4b12205a6c193 | |
| parent | 14bfd3c5c159626a2b3b8dec3a446e0f7c4c7e0c (diff) | |
| parent | 9e72046906bdb9a15054c6c54b0003bfdc3baf6e (diff) | |
| download | yosys-2c0d818296eda10f763287784b749a712bfeda98.tar.gz yosys-2c0d818296eda10f763287784b749a712bfeda98.tar.bz2 yosys-2c0d818296eda10f763287784b749a712bfeda98.zip | |
Merge branch 'master' of github.com:cliffordwolf/yosys
| -rw-r--r-- | passes/memory/memory_share.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index bcb7433a2..ca09ac52c 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -753,7 +753,7 @@ struct MemorySharePass : public Pass { log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { - log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n"); + log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n"); extra_args(args, 1, design); for (auto module : design->selected_modules()) MemoryShareWorker(design, module); |