diff options
author | Miodrag Milanovic <mmicko@gmail.com> | 2022-08-08 11:57:28 +0200 |
---|---|---|
committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-08-08 11:57:28 +0200 |
commit | 2b1aeb44d98f4aafc73a66cdd02092571d725ee4 (patch) | |
tree | d2433212366690a5c42c8f9a76e285949595b3a1 | |
parent | 60a787fa50062169c1aae4ecb199d13c0b6f25b6 (diff) | |
download | yosys-2b1aeb44d98f4aafc73a66cdd02092571d725ee4.tar.gz yosys-2b1aeb44d98f4aafc73a66cdd02092571d725ee4.tar.bz2 yosys-2b1aeb44d98f4aafc73a66cdd02092571d725ee4.zip |
verific - make filepath handling compatible with verilog frontend
-rw-r--r-- | frontends/verific/verific.cc | 44 |
1 files changed, 29 insertions, 15 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index ab527a253..e516a5ec7 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2828,9 +2828,11 @@ struct VerificPass : public Pass { for (auto &ext : verific_libexts) veri_file::AddLibExt(ext.c_str()); - while (argidx < GetSize(args)) - file_names.Insert(args[argidx++].c_str()); - + while (argidx < GetSize(args)) { + std::string filename(args[argidx++]); + rewrite_filename(filename); + file_names.Insert(strdup(filename.c_str())); + } if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU)) { verific_error_msg.clear(); log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); @@ -2843,36 +2845,48 @@ struct VerificPass : public Pass { #ifdef VERIFIC_VHDL_SUPPORT if (GetSize(args) > argidx && args[argidx] == "-vhdl87") { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str()); - for (argidx++; argidx < GetSize(args); argidx++) - if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_87)) - log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args[argidx].c_str()); + for (argidx++; argidx < GetSize(args); argidx++) { + std::string filename(args[argidx]); + rewrite_filename(filename); + if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_87)) + log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", filename.c_str()); + } verific_import_pending = true; goto check_error; } if (GetSize(args) > argidx && args[argidx] == "-vhdl93") { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str()); - for (argidx++; argidx < GetSize(args); argidx++) - if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_93)) - log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", args[argidx].c_str()); + for (argidx++; argidx < GetSize(args); argidx++) { + std::string filename(args[argidx]); + rewrite_filename(filename); + if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_93)) + log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", filename.c_str()); + } verific_import_pending = true; goto check_error; } if (GetSize(args) > argidx && args[argidx] == "-vhdl2k") { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str()); - for (argidx++; argidx < GetSize(args); argidx++) - if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_2K)) - log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", args[argidx].c_str()); + for (argidx++; argidx < GetSize(args); argidx++) { + std::string filename(args[argidx]); + rewrite_filename(filename); + if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2K)) + log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", filename.c_str()); + } verific_import_pending = true; goto check_error; } if (GetSize(args) > argidx && (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl")) { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str()); - for (argidx++; argidx < GetSize(args); argidx++) - if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_2008)) - log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", args[argidx].c_str()); + for (argidx++; argidx < GetSize(args); argidx++) { + std::string filename(args[argidx]); + rewrite_filename(filename); + if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2008)) + log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", filename.c_str()); + } verific_import_pending = true; goto check_error; } |