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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-27 13:24:19 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-27 13:24:19 +0200 |
| commit | 2a9c68e2d6e0d58ac9e1ef8e8eb4c21eb979b380 (patch) | |
| tree | e68672f6a6b667fc1561905ed1f0078c08cc81b7 | |
| parent | da140dd2602a049a94473f5f262189b22e19c185 (diff) | |
| parent | e3f9ccf56d65ba72dfa625e9716d1182f36a381e (diff) | |
| download | yosys-2a9c68e2d6e0d58ac9e1ef8e8eb4c21eb979b380.tar.gz yosys-2a9c68e2d6e0d58ac9e1ef8e8eb4c21eb979b380.tar.bz2 yosys-2a9c68e2d6e0d58ac9e1ef8e8eb4c21eb979b380.zip | |
Merge pull request #1026 from YosysHQ/clifford/fix1023
Keep zero-width wires in opt_clean if and only if they are ports
| -rw-r--r-- | kernel/log.cc | 9 | ||||
| -rw-r--r-- | passes/opt/opt_clean.cc | 5 |
2 files changed, 12 insertions, 2 deletions
diff --git a/kernel/log.cc b/kernel/log.cc index 9a9104e26..fa74a6a3c 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -230,6 +230,9 @@ static void logv_warning_with_prefix(const char *prefix, } else { + int bak_log_make_debug = log_make_debug; + log_make_debug = 0; + for (auto &re : log_werror_regexes) if (std::regex_search(message, re)) log_error("%s", message.c_str()); @@ -254,6 +257,7 @@ static void logv_warning_with_prefix(const char *prefix, } log_warnings_count++; + log_make_debug = bak_log_make_debug; } } @@ -285,6 +289,9 @@ static void logv_error_with_prefix(const char *prefix, #ifdef EMSCRIPTEN auto backup_log_files = log_files; #endif + int bak_log_make_debug = log_make_debug; + log_make_debug = 0; + log_suppressed(); if (log_errfile != NULL) log_files.push_back(log_errfile); @@ -298,6 +305,8 @@ static void logv_error_with_prefix(const char *prefix, log("%s%s", prefix, log_last_error.c_str()); log_flush(); + log_make_debug = bak_log_make_debug; + if (log_error_atexit) log_error_atexit(); diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index bf8020169..7011d4602 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -319,8 +319,9 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos wire->attributes.erase("\\init"); if (GetSize(wire) == 0) { - // delete zero-width wires - goto delete_this_wire; + // delete zero-width wires, unless they are module ports + if (wire->port_id == 0) + goto delete_this_wire; } else if (wire->port_id != 0 || wire->get_bool_attribute("\\keep") || !initval.is_fully_undef()) { // do not delete anything with "keep" or module ports or initialized wires |