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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 19:37:03 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 19:37:03 -0700 |
| commit | 242b72d4e11b815d0ca4fa80eee2e112333608d2 (patch) | |
| tree | 19556a99c8d66d81e4debb8ae7feffec63723c27 | |
| parent | 494610911ae2a5b2b73d0f5e030f237df56d3fb5 (diff) | |
| download | yosys-242b72d4e11b815d0ca4fa80eee2e112333608d2.tar.gz yosys-242b72d4e11b815d0ca4fa80eee2e112333608d2.tar.bz2 yosys-242b72d4e11b815d0ca4fa80eee2e112333608d2.zip | |
Fix simple_abc9/generate test with 1'bx at MSB
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index f652cdf12..3f7efa800 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -492,7 +492,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (w->port_output) { RTLIL::Wire *wire = module->wire(w->name); log_assert(wire); - for (int i = 0; i < GetSize(wire); i++) + for (int i = 0; i < GetSize(w); i++) output_bits.insert({wire, i}); } } |