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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-09 21:40:06 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-09 21:40:06 -0700 |
| commit | 1fc50a03fcaeebc0d1b12f397c2d31bcd27df715 (patch) | |
| tree | 131bbb1bf2e22e69a146a91de2b5bd059b9b0f3a | |
| parent | 02cf9933b9e5c0bff360db13c3577c0a75cdb5b9 (diff) | |
| download | yosys-1fc50a03fcaeebc0d1b12f397c2d31bcd27df715.tar.gz yosys-1fc50a03fcaeebc0d1b12f397c2d31bcd27df715.tar.bz2 yosys-1fc50a03fcaeebc0d1b12f397c2d31bcd27df715.zip | |
Add SIMD test
| -rw-r--r-- | tests/xilinx/dsp_simd.ys | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/tests/xilinx/dsp_simd.ys b/tests/xilinx/dsp_simd.ys new file mode 100644 index 000000000..956952327 --- /dev/null +++ b/tests/xilinx/dsp_simd.ys @@ -0,0 +1,25 @@ +read_verilog <<EOT +module simd(input [12*4-1:0] a, input [12*4-1:0] b, (* use_dsp="simd" *) output [7*12-1:0] o12, (* use_dsp="simd" *) output [2*24-1:0] o24); +generate + genvar i; + // 4 x 12-bit adder + for (i = 0; i < 4; i++) + assign o12[i*12+:12] = a[i*12+:12] + b[i*12+:12]; + // 2 x 24-bit subtract + for (i = 0; i < 2; i++) + assign o24[i*24+:24] = a[i*24+:24] - b[i*24+:24]; +endgenerate +reg [3*12-1:0] ro; +always @* begin + ro[0*12+:12] = a[0*10+:10] + b[0*10+:10]; + ro[1*12+:12] = a[1*10+:10] + b[1*10+:10]; + ro[2*12+:12] = a[2*8+:8] + b[2*8+:8]; +end +assign o12[4*12+:3*12] = ro; +endmodule +EOT + +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx +design -load postopt +select -assert-count 3 t:DSP48E1 |