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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-07 12:21:52 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-07 12:21:52 -0700 |
| commit | 1dc22607c38486d9e1a2b56f749d1eca35d405d2 (patch) | |
| tree | 503d667163bbc5c4bf7bbfaaebac3c01f12cffc9 | |
| parent | 1504ca2cd9211d9c4f31ecc262e347c842dc4fba (diff) | |
| download | yosys-1dc22607c38486d9e1a2b56f749d1eca35d405d2.tar.gz yosys-1dc22607c38486d9e1a2b56f749d1eca35d405d2.tar.bz2 yosys-1dc22607c38486d9e1a2b56f749d1eca35d405d2.zip | |
Remove -D_ABC9
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 07f3d9a8a..a99aef7c7 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -286,8 +286,6 @@ struct SynthXilinxPass : public ScriptPass std::string read_args; if (vpr) read_args += " -D_EXPLICIT_CARRY"; - if (abc9) - read_args += " -D_ABC9"; read_args += " -lib +/xilinx/cells_sim.v"; run("read_verilog" + read_args); |