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| author | Clifford Wolf <clifford@clifford.at> | 2015-09-24 11:21:20 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-09-24 11:21:20 +0200 |
| commit | 1b8cb9940e7c586b387cb212b4d9b9dbb881d62a (patch) | |
| tree | c0d23d4b82fbb0d13d90bfe3f480cb1fb7c45900 | |
| parent | e2e092b14406fdf0ad71bc2821fe2c880d927484 (diff) | |
| download | yosys-1b8cb9940e7c586b387cb212b4d9b9dbb881d62a.tar.gz yosys-1b8cb9940e7c586b387cb212b4d9b9dbb881d62a.tar.bz2 yosys-1b8cb9940e7c586b387cb212b4d9b9dbb881d62a.zip | |
Fixed AstNode::mkconst_bits() segfault on zero-sized constant
| -rw-r--r-- | frontends/ast/ast.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index a45859157..5044eeabc 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -699,7 +699,7 @@ AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signe for (size_t i = 0; i < 32; i++) { if (i < node->bits.size()) node->integer |= (node->bits[i] == RTLIL::S1) << i; - else if (is_signed) + else if (is_signed && !node->bits.empty()) node->integer |= (node->bits.back() == RTLIL::S1) << i; } node->range_valid = true; |