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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-01-31 13:45:28 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-01-31 13:45:28 +0100 |
| commit | 1b5ff92e6240c1a12cb3f28adb1b5d0dda77b6e7 (patch) | |
| tree | cffb31bd6b484b8278268bcda475e481bad74279 | |
| parent | eabd0ff11560e2d22d007a61010ac9231b413d37 (diff) | |
| download | yosys-1b5ff92e6240c1a12cb3f28adb1b5d0dda77b6e7.tar.gz yosys-1b5ff92e6240c1a12cb3f28adb1b5d0dda77b6e7.tar.bz2 yosys-1b5ff92e6240c1a12cb3f28adb1b5d0dda77b6e7.zip | |
Cleanup
| -rw-r--r-- | passes/sat/sim.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 34a56ff40..050fc8d5a 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -768,7 +768,6 @@ struct SimInstance retVal = true; } } - //log("signal: %s fst: %s sim: %s\n", log_id(item.first), log_signal(fst_val), log_signal(sim_val)); } for (auto child : children) retVal |= child.second->checkSignals(time); @@ -1048,6 +1047,7 @@ struct SimWorker : SimShared fst->reconstructAllAtTimes(edges); bool initial = false; int cycle = 0; + log("Co-simulation from %zu%s to %zu%s\n", startCount, fst->getTimescaleString(), stopCount, fst->getTimescaleString()); for(auto &time : edges) { log("Co-simulating cycle %d [%zu%s].\n", cycle+1, time, fst->getTimescaleString()); for(auto &item : inputs) { |