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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 15:23:26 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 15:23:26 -0700 |
| commit | 1b5d2de1d4212bd93f9b0ca0d5173e4c8a4dd4e8 (patch) | |
| tree | d94c2c971235b004645d5cde7dd986dbfaeb6d4c | |
| parent | 0ca397f087287307d13daac57f60c24c6f2a982e (diff) | |
| download | yosys-1b5d2de1d4212bd93f9b0ca0d5173e4c8a4dd4e8.tar.gz yosys-1b5d2de1d4212bd93f9b0ca0d5173e4c8a4dd4e8.tar.bz2 yosys-1b5d2de1d4212bd93f9b0ca0d5173e4c8a4dd4e8.zip | |
Do not sigmap!
| -rw-r--r-- | backends/aiger/xaiger.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index ad2a778fa..d02997da4 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -355,7 +355,7 @@ struct XAigerWriter log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type)); if (is_input) { - for (auto b : sigmap(c.second)) { + for (auto b : c.second) { Wire *w = b.wire; if (!w) continue; if (!w->port_output || !cell_known) { @@ -381,7 +381,7 @@ struct XAigerWriter } } - for (auto b : sigmap(c.second)) { + for (auto b : c.second) { Wire *w = b.wire; if (!w) continue; input_bits.insert(b); |