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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-01-31 08:56:29 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-01-31 08:56:29 +0100 |
| commit | 190e44f0dac1a9c7f2dbf0c3069cd1d646806aaa (patch) | |
| tree | 1812d26aa7004eeac77e005eaeb1bff0c21bcba8 | |
| parent | f04d1398e569d6371a6f31c34ff145096d4a96c9 (diff) | |
| download | yosys-190e44f0dac1a9c7f2dbf0c3069cd1d646806aaa.tar.gz yosys-190e44f0dac1a9c7f2dbf0c3069cd1d646806aaa.tar.bz2 yosys-190e44f0dac1a9c7f2dbf0c3069cd1d646806aaa.zip | |
Fix scope
| -rw-r--r-- | passes/sat/sim.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 3cf5967cc..bea8f12b4 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -194,7 +194,7 @@ struct SimInstance Module *mod = module->design->module(cell->type); if (mod != nullptr) { - dirty_children.insert(new SimInstance(shared, scope + "." + RTLIL::unescape_id(module->name), mod, cell, this)); + dirty_children.insert(new SimInstance(shared, scope + "." + RTLIL::unescape_id(cell->name), mod, cell, this)); } for (auto &port : cell->connections()) { |