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author | Clifford Wolf <clifford@clifford.at> | 2013-11-07 03:01:28 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-11-07 03:01:28 +0100 |
commit | 160adccca2cc8f81c2937cab03280603aaafb391 (patch) | |
tree | d9cc949bd7cd4cd19fce3f12cc70b98e8a8f0796 | |
parent | 404b46674b3bfec73ecac484bbf56354fd66f2c8 (diff) | |
download | yosys-160adccca2cc8f81c2937cab03280603aaafb391.tar.gz yosys-160adccca2cc8f81c2937cab03280603aaafb391.tar.bz2 yosys-160adccca2cc8f81c2937cab03280603aaafb391.zip |
Fixed the fix for propagation of width hints for $signed() and $unsigned()
-rw-r--r-- | frontends/ast/genrtlil.cc | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index ce34f708a..0fde9b3b9 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -947,13 +947,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) return sig; } - // just pass thru the signal. the parent will evaluated the is_signed property and inperpret the SigSpec accordingly + // just pass thru the signal. the parent will evaluate the is_signed property and inperpret the SigSpec accordingly case AST_TO_SIGNED: case AST_TO_UNSIGNED: { - int sub_width_hint; - bool sub_sign_hint; - children[0]->detectSignWidth(sub_width_hint, sub_sign_hint); - RTLIL::SigSpec sig = children[0]->genRTLIL(width_hint, sub_sign_hint); + RTLIL::SigSpec sig = children[0]->genRTLIL(); + if (sig.width < width_hint) + sig.extend(width_hint, sign_hint); is_signed = sign_hint; return sig; } |