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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-25 18:08:05 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-25 18:08:05 -0700 |
| commit | 0eb7150a5706e81ff36a6a57d8c0c6a2fda05e07 (patch) | |
| tree | bf386a284216c17e986edfe7a272185f7bec67b3 | |
| parent | af3c374a3589994c41ebd5fcfc75f292dbd7e602 (diff) | |
| download | yosys-0eb7150a5706e81ff36a6a57d8c0c6a2fda05e07.tar.gz yosys-0eb7150a5706e81ff36a6a57d8c0c6a2fda05e07.tar.bz2 yosys-0eb7150a5706e81ff36a6a57d8c0c6a2fda05e07.zip | |
Add test
| -rw-r--r-- | tests/various/split_shiftx.v | 118 | ||||
| -rw-r--r-- | tests/various/split_shiftx.ys | 21 |
2 files changed, 139 insertions, 0 deletions
diff --git a/tests/various/split_shiftx.v b/tests/various/split_shiftx.v new file mode 100644 index 000000000..dfcea3880 --- /dev/null +++ b/tests/various/split_shiftx.v @@ -0,0 +1,118 @@ +module split_shiftx_test01(i, s, o); + wire [3:0] _0_; + input [8:0] i; + output [2:0] o; + input [1:0] s; + \$macc #( + .A_WIDTH(32'd4), + .B_WIDTH(32'd0), + .CONFIG(10'h282), + .CONFIG_WIDTH(32'd10), + .Y_WIDTH(32'd4) + ) _1_ ( + .A({ 2'h3, s }), + .B(), + .Y(_0_) + ); + \$shiftx #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd9), + .B_SIGNED(32'd1), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd3) + ) _2_ ( + .A(i), + .B({ 1'h0, _0_ }), + .Y(o) + ); +endmodule + +// Sign bit is 1 +module split_shiftx_test02(i, s, o); + wire [3:0] _0_; + input [8:0] i; + output [2:0] o; + input [1:0] s; + \$macc #( + .A_WIDTH(32'd4), + .B_WIDTH(32'd0), + .CONFIG(10'h282), + .CONFIG_WIDTH(32'd10), + .Y_WIDTH(32'd4) + ) _1_ ( + .A({ 2'h3, s }), + .B(), + .Y(_0_) + ); + \$shiftx #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd9), + .B_SIGNED(32'd1), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd3) + ) _2_ ( + .A(i), + .B({ 1'h1, _0_ }), + .Y(o) + ); +endmodule + +// Non constant $macc +module split_shiftx_test03(i, s, o); + wire [3:0] _0_; + input [8:0] i; + output [2:0] o; + input [1:0] s; + \$macc #( + .A_WIDTH(32'd4), + .B_WIDTH(32'd0), + .CONFIG(10'h282), + .CONFIG_WIDTH(32'd10), + .Y_WIDTH(32'd4) + ) _1_ ( + .A({ s, s }), + .B(), + .Y(_0_) + ); + \$shiftx #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd9), + .B_SIGNED(32'd1), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd3) + ) _2_ ( + .A(i), + .B({ 1'h0, _0_ }), + .Y(o) + ); +endmodule + +// Wrong constant $macc +module split_shiftx_test04(i, s, o); + wire [3:0] _0_; + input [8:0] i; + output [2:0] o; + input [1:0] s; + \$macc #( + .A_WIDTH(32'd4), + .B_WIDTH(32'd0), + .CONFIG(10'h282), + .CONFIG_WIDTH(32'd10), + .Y_WIDTH(32'd4) + ) _1_ ( + .A({ 2'h2, s }), + .B(), + .Y(_0_) + ); + \$shiftx #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd9), + .B_SIGNED(32'd1), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd3) + ) _2_ ( + .A(i), + .B({ 1'h0, _0_ }), + .Y(o) + ); +endmodule diff --git a/tests/various/split_shiftx.ys b/tests/various/split_shiftx.ys new file mode 100644 index 000000000..810348aa3 --- /dev/null +++ b/tests/various/split_shiftx.ys @@ -0,0 +1,21 @@ +read_verilog -icells split_shiftx.v +split_shiftx + +cd split_shiftx_test01 +select -assert-count 3 t:$shiftx +select -assert-count 0 t: t:$shiftx %n %i + +cd split_shiftx_test02 +select -assert-count 1 t:$shiftx +select -assert-count 1 t:$macc +select -assert-count 0 t: t:$shiftx t:$macc %u %n %i + +cd split_shiftx_test03 +select -assert-count 1 t:$shiftx +select -assert-count 1 t:$macc +select -assert-count 0 t: t:$shiftx t:$macc %u %n %i + +cd split_shiftx_test04 +select -assert-count 1 t:$shiftx +select -assert-count 1 t:$macc +select -assert-count 0 t: t:$shiftx t:$macc %u %n %i |