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| author | Jannis Harder <me@jix.one> | 2022-06-29 20:02:12 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-06-29 20:02:12 +0200 |
| commit | 0d2377c8a6face25a83f15929e02ce62d99da005 (patch) | |
| tree | 6ff3de4c2948b79579ec49bd2818864762b933e1 | |
| parent | 869e6a1b6d463ff1e72e8ae57cae751be4000687 (diff) | |
| parent | 930bcf0e75f3b8d6c5afbdffda5ef7fd7eddc964 (diff) | |
| download | yosys-0d2377c8a6face25a83f15929e02ce62d99da005.tar.gz yosys-0d2377c8a6face25a83f15929e02ce62d99da005.tar.bz2 yosys-0d2377c8a6face25a83f15929e02ce62d99da005.zip | |
Merge pull request #3394 from jix/memory_map_rom_keepdc
memory_map: -keepdc option for formal
| -rw-r--r-- | backends/btor/btor.cc | 1 | ||||
| -rw-r--r-- | backends/smt2/smt2.cc | 1 | ||||
| -rw-r--r-- | passes/memory/memory_map.cc | 20 |
3 files changed, 17 insertions, 5 deletions
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 7dec70545..831a3ada2 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -1405,7 +1405,6 @@ struct BtorBackend : public Backend { log_header(design, "Executing BTOR backend.\n"); log_push(); - Pass::call(design, "memory_map -rom-only"); Pass::call(design, "bmuxmap"); Pass::call(design, "demuxmap"); log_pop(); diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index 6e70f9043..7481e0510 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -1609,7 +1609,6 @@ struct Smt2Backend : public Backend { log_header(design, "Executing SMT2 backend.\n"); log_push(); - Pass::call(design, "memory_map -rom-only"); Pass::call(design, "bmuxmap"); Pass::call(design, "demuxmap"); log_pop(); diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index ccfb8c94f..fd5b1f1ad 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -31,6 +31,7 @@ struct MemoryMapWorker { bool attr_icase = false; bool rom_only = false; + bool keepdc = false; dict<RTLIL::IdString, std::vector<RTLIL::Const>> attributes; RTLIL::Design *design; @@ -190,14 +191,15 @@ struct MemoryMapWorker { int addr = i + mem.start_offset; int idx = addr & ((1 << abits) - 1); + SigSpec w_init = init_data.extract(i*mem.width, mem.width); if (static_cells_map.count(addr) > 0) { data_reg_out[idx] = static_cells_map[addr]; count_static++; } - else if (mem.wr_ports.empty()) + else if (mem.wr_ports.empty() && (!keepdc || w_init.is_fully_def())) { - data_reg_out[idx] = init_data.extract(i*mem.width, mem.width); + data_reg_out[idx] = w_init; } else { @@ -220,13 +222,15 @@ struct MemoryMapWorker w_out_name = genid(mem.memid, "", addr, "$q"); RTLIL::Wire *w_out = module->addWire(w_out_name, mem.width); - SigSpec w_init = init_data.extract(i*mem.width, mem.width); if (!w_init.is_fully_undef()) w_out->attributes[ID::init] = w_init.as_const(); data_reg_out[idx] = w_out; c->setPort(ID::Q, w_out); + + if (mem.wr_ports.empty()) + module->connect(RTLIL::SigSig(w_in, w_out)); } } @@ -380,11 +384,15 @@ struct MemoryMapPass : public Pass { log(" -rom-only\n"); log(" only perform conversion for ROMs (memories with no write ports).\n"); log("\n"); + log(" -keepdc\n"); + log(" when mapping ROMs, keep x-bits shared across read ports.\n"); + log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) override { bool attr_icase = false; bool rom_only = false; + bool keepdc = false; dict<RTLIL::IdString, std::vector<RTLIL::Const>> attributes; log_header(design, "Executing MEMORY_MAP pass (converting memories to logic and flip-flops).\n"); @@ -426,6 +434,11 @@ struct MemoryMapPass : public Pass { rom_only = true; continue; } + if (args[argidx] == "-keepdc") + { + keepdc = true; + continue; + } break; } extra_args(args, argidx, design); @@ -435,6 +448,7 @@ struct MemoryMapPass : public Pass { worker.attr_icase = attr_icase; worker.attributes = attributes; worker.rom_only = rom_only; + worker.keepdc = keepdc; worker.run(); } } |