diff options
| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-25 15:31:52 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-25 15:31:52 -0800 |
| commit | 0ca3fd6a1cca6f12db4069ed6f73b814aee2eeaf (patch) | |
| tree | abcf2ceb99466915c4211d9efcb66262228f5151 | |
| parent | 292f80d231174951b8ebda5b1f9b70b6b95a545a (diff) | |
| download | yosys-0ca3fd6a1cca6f12db4069ed6f73b814aee2eeaf.tar.gz yosys-0ca3fd6a1cca6f12db4069ed6f73b814aee2eeaf.tar.bz2 yosys-0ca3fd6a1cca6f12db4069ed6f73b814aee2eeaf.zip | |
abc9 not to clean after aigmap
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index f6ace6a94..90234ea33 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -403,7 +403,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::Selection& sel = design->selection_stack.back(); sel.select(module); - Pass::call(design, "aigmap; clean;"); + Pass::call(design, "aigmap"); handle_loops(design); |