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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 16:23:15 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 16:23:15 -0700 |
| commit | 0ab8f28bc7b6fefc1b4acd4e5c1cb437af878806 (patch) | |
| tree | 55f5049c21e4d478dce2c48b8c165e19be03e1b2 | |
| parent | 838ae1a14cddf25919bb2a68e74220a07db4a06e (diff) | |
| download | yosys-0ab8f28bc7b6fefc1b4acd4e5c1cb437af878806.tar.gz yosys-0ab8f28bc7b6fefc1b4acd4e5c1cb437af878806.tar.bz2 yosys-0ab8f28bc7b6fefc1b4acd4e5c1cb437af878806.zip | |
Uncomment IS_C_INVERTED parameter
| -rw-r--r-- | techlibs/xilinx/abc_ff.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v index 8bbdff6f4..d81f828e9 100644 --- a/techlibs/xilinx/abc_ff.v +++ b/techlibs/xilinx/abc_ff.v @@ -26,7 +26,7 @@ endmodule (* abc_box_id = 8, lib_whitebox, abc_flop = "FDRE,D,Q,\\$pastQ" *) module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ ); parameter [0:0] INIT = 1'b0; - //parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_R_INVERTED = 1'b0; assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ ); |