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authorMiodrag Milanovic <mmicko@gmail.com>2020-06-29 14:42:48 +0200
committerMiodrag Milanovic <mmicko@gmail.com>2020-06-29 14:42:48 +0200
commit0545a042f363efe1c1543d2b85269efe394c830f (patch)
tree538a30fe2cb33a1eb9e30cb9d20022c2a43b7fa3
parent87717d67d1bf24e0fa120a16dda71a47b33fa347 (diff)
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cleanup
-rw-r--r--passes/sat/expose.cc25
1 files changed, 13 insertions, 12 deletions
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index e115b184e..20b8536fc 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -479,21 +479,15 @@ struct ExposePass : public Pass {
}
}
}
- for (auto &wm : wire_map)
- {
- if (flag_input) {
- RTLIL::Wire *in_wire = module->addWire(wm.second, GetSize(wm.first));
- out_to_in_map.add(wm.first, in_wire);
- }
- if (flag_cut) {
- RTLIL::Wire *in_wire = add_new_wire(module, wm.second, wm.first->width);
- in_wire->port_input = true;
- out_to_in_map.add(sigmap(wm.first), in_wire);
- }
- }
if (flag_input)
{
+ for (auto &wm : wire_map)
+ {
+ RTLIL::Wire *in_wire = module->addWire(wm.second, GetSize(wm.first));
+ out_to_in_map.add(wm.first, in_wire);
+ }
+
for (auto cell : module->cells()) {
if (!ct.cell_known(cell->type))
continue;
@@ -508,6 +502,13 @@ struct ExposePass : public Pass {
if (flag_cut)
{
+ for (auto &wm : wire_map)
+ {
+ RTLIL::Wire *in_wire = add_new_wire(module, wm.second, wm.first->width);
+ in_wire->port_input = true;
+ out_to_in_map.add(sigmap(wm.first), in_wire);
+ }
+
for (auto cell : module->cells()) {
if (!ct.cell_known(cell->type))
continue;