intel: move Cyclone V support to intel_alm

7 files changed, 11 insertions, 203 deletions

diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc
index fef6aab77..0c4899f06 100644
--- a/techlibs/intel/Makefile.inc
+++ b/techlibs/intel/Makefile.inc
@@ -8,7 +8,7 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_
 $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/ff_map.v))
 
 # Add the cell models and mappings for the VQM backend
-families := max10 arria10gx cyclonev cyclone10lp cycloneiv cycloneive
+families := max10 arria10gx cyclone10lp cycloneiv cycloneive
 $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v)))
 $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v)))
 #$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v))
diff --git a/techlibs/intel/cyclonev/cells_arith.v b/techlibs/intel/cyclonev/cells_arith.v
deleted file mode 100644
index 6a52a0f95..000000000
--- a/techlibs/intel/cyclonev/cells_arith.v
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- *  yosys -- Yosys Open SYnthesis Suite
- *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-// NOTE: This is still WIP.
-(* techmap_celltype = "$alu" *)
-module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
-   parameter A_SIGNED = 0;
-   parameter B_SIGNED = 0;
-   parameter A_WIDTH  = 1;
-   parameter B_WIDTH  = 1;
-   parameter Y_WIDTH  = 1;
-
-	(* force_downto *)
-	input [A_WIDTH-1:0] A;
-	(* force_downto *)
-	input [B_WIDTH-1:0] B;
-	(* force_downto *)
-	output [Y_WIDTH-1:0] X, Y;
-
-	input CI, BI;
-	//output [Y_WIDTH-1:0] CO;
-        output                 CO;
-
-	wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
-
-	(* force_downto *)
-	wire [Y_WIDTH-1:0] A_buf, B_buf;
-	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
-	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
-
-	(* force_downto *)
-	wire [Y_WIDTH-1:0] AA = A_buf;
-	(* force_downto *)
-	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
-	//wire [Y_WIDTH:0] C = {CO, CI};
-        wire [Y_WIDTH+1:0] COx;
-        wire [Y_WIDTH+1:0] C = {COx, CI};
-
-	/* Start implementation */
-	(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
-
-	genvar i;
-	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
-	  if(i==Y_WIDTH-1) begin
-	    (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
-            assign CO = COx[Y_WIDTH];
-          end
-	  else
-	    fiftyfivenm_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
-	  end: slice
-	endgenerate
-	/* End implementation */
-	assign X = AA ^ BB;
-
-endmodule
diff --git a/techlibs/intel/cyclonev/cells_map.v b/techlibs/intel/cyclonev/cells_map.v
deleted file mode 100644
index 0041481ab..000000000
--- a/techlibs/intel/cyclonev/cells_map.v
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- *  yosys -- Yosys Open SYnthesis Suite
- *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
-// > Intel FPGA technology mapping. User must first simulate the generated \
-// > netlist before going to test it on board.
-
-// Input buffer map
-module \$__inpad (input I, output O);
-   cyclonev_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
-endmodule
-
-// Output buffer map
-module \$__outpad (input I, output O);
-   cyclonev_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
-endmodule
-
-// LUT Map
-module \$lut (A, Y);
-   parameter WIDTH  = 0;
-   parameter LUT    = 0;
-   (* force_downto *)
-   input [WIDTH-1:0] A;
-   output            Y;
-   wire              VCC;
-   wire              GND;
-   assign {VCC,GND} = {1'b1,1'b0};
-
-   generate
-      if (WIDTH == 1) begin
-	 assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
-      end
-      else
-        if (WIDTH == 2) begin
-           cyclonev_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
-           _TECHMAP_REPLACE_
-             (.combout(Y),
-              .dataa(A[0]),
-              .datab(A[1]),
-              .datac(VCC),
-              .datad(VCC),
-              .datae(VCC),
-              .dataf(VCC),
-              .datag(VCC));
-        end
-        else
-          if(WIDTH == 3) begin
-	     cyclonev_lcell_comb #(.lut_mask({8{LUT}}), .shared_arith("off"), .extended_lut("off"))
-             _TECHMAP_REPLACE_
-               (.combout(Y),
-                .dataa(A[0]),
-                .datab(A[1]),
-                .datac(A[2]),
-                .datad(VCC),
-                .datae(VCC),
-                .dataf(VCC),
-                .datag(VCC));
-          end
-          else
-            if(WIDTH == 4) begin
-	       cyclonev_lcell_comb #(.lut_mask({4{LUT}}), .shared_arith("off"), .extended_lut("off"))
-               _TECHMAP_REPLACE_
-                 (.combout(Y),
-                  .dataa(A[0]),
-                  .datab(A[1]),
-                  .datac(A[2]),
-                  .datad(A[3]),
-                  .datae(VCC),
-                  .dataf(VCC),
-                  .datag(VCC));
-            end
-            else
-              if(WIDTH == 5) begin
-                 cyclonev_lcell_comb #(.lut_mask({2{LUT}}), .shared_arith("off"), .extended_lut("off"))
-                 _TECHMAP_REPLACE_
-                   (.combout(Y),
-                    .dataa(A[0]),
-                    .datab(A[1]),
-                    .datac(A[2]),
-                    .datad(A[3]),
-                    .datae(A[4]),
-                    .dataf(VCC),
-                    .datag(VCC));
-              end
-              else
-                if(WIDTH == 6) begin
-                   cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off"))
-                   _TECHMAP_REPLACE_
-                     (.combout(Y),
-                      .dataa(A[0]),
-                      .datab(A[1]),
-                      .datac(A[2]),
-                      .datad(A[3]),
-                      .datae(A[4]),
-                      .dataf(A[5]),
-                      .datag(VCC));
-                end
-                /*else
-                  if(WIDTH == 7) begin
-                    TODO: There's not a just 7-input function on Cyclone V, see the following note:
-                    **Extended LUT Mode**
-                    Use extended LUT mode to implement a specific set of 7-input functions. The set must
-                    be a 2-to-1 multiplexer fed by two arbitrary 5-input functions sharing four inputs.
-                    [source](Device Interfaces and Integration Basics for Cyclone V Devices).
-                  end*/
-                  else
-                     wire _TECHMAP_FAIL_ = 1;
-   endgenerate
-endmodule // lut
-
-
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 090237722..31372f0e8 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -36,11 +36,11 @@ struct SynthIntelPass : public ScriptPass {
 		log("\n");
 		log("This command runs synthesis for Intel FPGAs.\n");
 		log("\n");
-		log("    -family <max10 | arria10gx | cyclone10lp | cyclonev | cycloneiv | cycloneive>\n");
+		log("    -family <max10 | arria10gx | cyclone10lp | cycloneiv | cycloneive>\n");
 		log("        generate the synthesis netlist for the specified family.\n");
 		log("        MAX10 is the default target if no family argument specified.\n");
 		log("        For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.\n");
-		log("        Cyclone V and Arria 10 GX devices are experimental.\n");
+		log("        Arria 10 GX devices are experimental.\n");
 		log("\n");
 		log("    -top <module>\n");
 		log("        use the specified module as top module (default='top')\n");
@@ -147,9 +147,12 @@ struct SynthIntelPass : public ScriptPass {
 
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
+
+		if (family_opt == "cyclonev")
+			log_cmd_error("Cyclone V synthesis has been moved to synth_intel_alm.\n");
+
 		if (family_opt != "max10" &&
 		    family_opt != "arria10gx" &&
-		    family_opt != "cyclonev" &&
 		    family_opt != "cycloneiv" &&
 		    family_opt != "cycloneive" &&
 		    family_opt != "cyclone10lp")
@@ -216,7 +219,7 @@ struct SynthIntelPass : public ScriptPass {
 		}
 
 		if (check_label("map_luts")) {
-			if (family_opt == "arria10gx" || family_opt == "cyclonev")
+			if (family_opt == "arria10gx")
 				run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
 			else
 				run("abc -lut 4" + string(retime ? " -dff" : ""));
diff --git a/techlibs/intel_alm/Makefile.inc b/techlibs/intel_alm/Makefile.inc
index e36c81c0e..da88762c4 100644
--- a/techlibs/intel_alm/Makefile.inc
+++ b/techlibs/intel_alm/Makefile.inc
@@ -14,6 +14,8 @@ $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/ds
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dsp_map.v))
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/mem_sim.v))
 
+$(eval $(call add_share_file,share/intel_alm/cyclonev,techlibs/intel_alm/cyclonev/cells_sim.v))
+
 # RAM
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k.txt))
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m20k.txt))
diff --git a/techlibs/intel/cyclonev/cells_sim.v b/techlibs/intel_alm/cyclonev/cells_sim.v
index 9b2a10e72..9b2a10e72 100644
--- a/techlibs/intel/cyclonev/cells_sim.v
+++ b/techlibs/intel_alm/cyclonev/cells_sim.v
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc
index 83f0768a3..7ab50ef8f 100644
--- a/techlibs/intel_alm/synth_intel_alm.cc
+++ b/techlibs/intel_alm/synth_intel_alm.cc
@@ -178,7 +178,7 @@ struct SynthIntelALMPass : public ScriptPass {
 
 		if (check_label("begin")) {
 			if (family_opt == "cyclonev")
-				run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str()));
+				run(stringf("read_verilog -sv -lib +/intel_alm/%s/cells_sim.v", family_opt.c_str()));
 			run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt.c_str()));
 			run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt.c_str()));
 			run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dsp_sim.v", family_opt.c_str()));