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* mistral: add M10K belLofty2022-03-091-0/+1
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* run clangformatgatecat2022-02-031-2/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Mistral: Use log_error, remove leftover debugging printf.Olivier Galibert2022-01-191-36/+3
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* Mistral: fix gpio OE, add hmc bypass supportOlivier Galibert2022-01-181-1/+33
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* Sync with the current state of mistralOlivier Galibert2022-01-181-1/+0
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* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-191-1/+1
| | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add internal oscillator supportOlivier Galibert2021-10-171-3/+4
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* mistral: Add support for cyclonev_hps_interface_mpu_general_purposeOlivier Galibert2021-10-141-0/+1
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* clangformatgatecat2021-10-111-3/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: very basic timing infoLofty2021-10-101-1/+5
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* mistral: Adding support for MLABs as memorygatecat2021-10-051-0/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Use MLABs as if they're LABs (for now)Lofty2021-08-171-3/+5
| | | | Signed-off-by: Lofty <dan.ravensloft@gmail.com>
* mistral: Fix pip binding checkgatecat2021-08-141-4/+11
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Remove mistral root argumentgatecat2021-06-041-1/+0
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Using hashlib in archesgatecat2021-06-021-15/+14
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Fix nextpnr build with LLVMgatecat2021-06-021-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: add getChipNameLofty2021-05-151-1/+1
| | | | Signed-off-by: Lofty <dan.ravensloft@gmail.com>
* mistral: Add MISTRAL_CLKBUF cell typegatecat2021-05-151-0/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Tidying upgatecat2021-05-151-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Speed up bel binding and checkinggatecat2021-05-151-4/+18
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Fix ENA and ACLR bitstream generationgatecat2021-05-151-0/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Account for TD input count limitgatecat2021-05-151-3/+23
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Implement PIP locations, toogatecat2021-05-151-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Implement bounding boxes for router2gatecat2021-05-151-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Adding FF control set reservationgatecat2021-05-151-7/+27
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add stub RBF generationgatecat2021-05-151-0/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Implement some misc. thingsgatecat2021-05-151-7/+14
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Some preps for generating bitstreamsgatecat2021-05-151-0/+12
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Adding a function for computing ALM LUT masksgatecat2021-05-151-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add IO packinggatecat2021-05-151-1/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add a basic QSF parsergatecat2021-05-151-0/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add the 'pin style' stuff based on Nexusgatecat2021-05-151-0/+45
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Working on ALM input assignmentgatecat2021-05-151-1/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add stub pack/place/route functionsgatecat2021-05-151-0/+11
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Renamed arch from cyclonevgatecat2021-05-151-0/+405
Signed-off-by: gatecat <gatecat@ds0.me>