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author | Olivier Galibert <galibert@pobox.com> | 2022-01-19 08:42:29 +0100 |
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committer | Olivier Galibert <galibert@pobox.com> | 2022-01-19 08:42:29 +0100 |
commit | 27d38de612ce4109723704f863ac82a6cbddf10c (patch) | |
tree | 9f0aa005ecfbb5a22a14c377a3d663465639a5a7 /mistral/arch.h | |
parent | 91a0eb93672e9c764f03fd1b0a7d22595a61c516 (diff) | |
download | nextpnr-27d38de612ce4109723704f863ac82a6cbddf10c.tar.gz nextpnr-27d38de612ce4109723704f863ac82a6cbddf10c.tar.bz2 nextpnr-27d38de612ce4109723704f863ac82a6cbddf10c.zip |
Mistral: Use log_error, remove leftover debugging printf.
Diffstat (limited to 'mistral/arch.h')
-rw-r--r-- | mistral/arch.h | 39 |
1 files changed, 3 insertions, 36 deletions
diff --git a/mistral/arch.h b/mistral/arch.h index 98340d4e..e931df2d 100644 --- a/mistral/arch.h +++ b/mistral/arch.h @@ -461,42 +461,9 @@ struct Arch : BaseArch<ArchRanges> void add_bel_pin(BelId bel, IdString pin, PortType dir, WireId wire); - CycloneV::rnode_t find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi = -1, int pi = -1) const - { - auto pn1 = CycloneV::pnode(bt, x, y, port, bi, pi); - auto rn1 = cyclonev->pnode_to_rnode(pn1); - if(rn1) - return rn1; - - if(bt == CycloneV::GPIO) { - auto pn2 = cyclonev->p2p_to(pn1); - if(!pn2) { - auto pnv = cyclonev->p2p_from(pn1); - if(!pnv.empty()) - pn2 = pnv[0]; - } - auto pn3 = cyclonev->hmc_get_bypass(pn2); - auto rn2 = cyclonev->pnode_to_rnode(pn3); - return rn2; - } - - return 0; - } - - WireId get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const - { - auto rn = find_rnode(bt, x, y, port, bi, pi); - if(rn) - return WireId(rn); - - fprintf(stderr, "Trying to connect unknown node %s\n", CycloneV::pn2s(CycloneV::pnode(bt, x, y, port, bi, pi)).c_str()); - exit(1); - } - - bool has_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const - { - return find_rnode(bt, x, y, port, bi, pi) != 0; - } + CycloneV::rnode_t find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi = -1, int pi = -1) const; + WireId get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const; + bool has_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const; void create_lab(int x, int y, bool is_mlab); // lab.cc void create_gpio(int x, int y); // io.cc |