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* mistral: Remove mistral root argumentgatecat2021-06-041-1/+0
* Using hashlib in archesgatecat2021-06-021-15/+14
* mistral: Fix nextpnr build with LLVMgatecat2021-06-021-1/+1
* mistral: add getChipNameLofty2021-05-151-1/+1
* mistral: Add MISTRAL_CLKBUF cell typegatecat2021-05-151-0/+4
* mistral: Tidying upgatecat2021-05-151-1/+1
* mistral: Speed up bel binding and checkinggatecat2021-05-151-4/+18
* mistral: Fix ENA and ACLR bitstream generationgatecat2021-05-151-0/+1
* mistral: Account for TD input count limitgatecat2021-05-151-3/+23
* mistral: Implement PIP locations, toogatecat2021-05-151-1/+1
* mistral: Implement bounding boxes for router2gatecat2021-05-151-1/+1
* mistral: Adding FF control set reservationgatecat2021-05-151-7/+27
* mistral: Add stub RBF generationgatecat2021-05-151-0/+1
* mistral: Implement some misc. thingsgatecat2021-05-151-7/+14
* mistral: Some preps for generating bitstreamsgatecat2021-05-151-0/+12
* mistral: Adding a function for computing ALM LUT masksgatecat2021-05-151-0/+2
* mistral: Add IO packinggatecat2021-05-151-1/+4
* mistral: Add a basic QSF parsergatecat2021-05-151-0/+4
* mistral: Add the 'pin style' stuff based on Nexusgatecat2021-05-151-0/+45
* mistral: Working on ALM input assignmentgatecat2021-05-151-1/+2
* mistral: Add stub pack/place/route functionsgatecat2021-05-151-0/+11
* mistral: Renamed arch from cyclonevgatecat2021-05-151-0/+405
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