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* Add binary search to getBelPinWire() and getBelPinType()Clifford Wolf2018-07-313-16/+43
* Towards better ice40 timing dataClifford Wolf2018-07-301-7/+21
* Use DelayInfo for cell timing instead of delay_tDavid Shah2018-07-302-8/+8
* cmake: Set --fast and --slow chipdb.py argumentsDavid Shah2018-07-302-3/+24
* Add ice40 chipdb.py --fast/--slowClifford Wolf2018-07-301-0/+30
* Add iCE40 fast/slow delay fields to chipdbClifford Wolf2018-07-303-5/+29
* ice40: Improving legalisation move statisticsDavid Shah2018-07-301-2/+5
* ice40: Print legalisation statisticsDavid Shah2018-07-301-0/+39
* Improve ice40/benchmarkClifford Wolf2018-07-302-11/+35
* common: rename GraphicElement::{style,type} enums, add _MAX membersSergiusz Bazanski2018-07-263-19/+19
* clangformat and GraphicElement::style commentsClifford Wolf2018-07-261-2/+2
* Add getWireType()/getPipType() APIClifford Wolf2018-07-261-0/+4
* Move iCE40 switchbox gfx to UI groupsClifford Wolf2018-07-261-93/+162
* Add iCE40 pip gfx for carry_in muxClifford Wolf2018-07-261-0/+11
* Improvements in bbasmClifford Wolf2018-07-261-1/+2
* clangformatEddie Hung2018-07-253-15/+12
* Merge remote-tracking branch 'origin/master' into eddieh/idstring_speedupEddie Hung2018-07-2515-289/+4388
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| * Add ice40/benchmark/report.ipynbClifford Wolf2018-07-251-0/+69
| * More minor ice40 benchmark improvementsClifford Wolf2018-07-252-2/+7
| * ice40: Tweaking picorv32_benchmark.pyDavid Shah2018-07-251-2/+1
| * Minor improvements in iCE40 benchmark scriptsClifford Wolf2018-07-252-2/+7
| * Add ice40/benchmark/Clifford Wolf2018-07-257-0/+4136
| * Merge branch 'bba' into 'master'Clifford Wolf2018-07-252-277/+42
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| | * proper options for linux buildMiodrag Milanovic2018-07-251-1/+1
| | * Use bbasm to create iCE40 chipdbClifford Wolf2018-07-242-277/+42
| * | ice40: after reviewSergiusz Bazanski2018-07-252-3/+3
| * | ice40: check PLL PACKAGEPIN drives only PLL, cosmeticsSergiusz Bazanski2018-07-251-4/+7
| * | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/pll-padsSergiusz Bazanski2018-07-251-0/+43
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| | * | Add a simple 8x benchmark scriptDavid Shah2018-07-251-0/+43
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| * | clang-formatSergiusz Bazanski2018-07-251-7/+7
| * | ice40: support PLL40_*_PAD, fix pass-through LUT for LOCKSergiusz Bazanski2018-07-253-7/+81
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* / Reduce id() lookups for commonly used update_budget()Eddie Hung2018-07-243-24/+33
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* ice40: after reviewSergiusz Bazanski2018-07-241-1/+0
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/pllSergiusz Bazanski2018-07-249-85/+44
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| * Remove implementations of deprecated APIsDavid Shah2018-07-243-30/+0
| * ice40: Remove use of deprecated APIsDavid Shah2018-07-243-10/+10
| * Remove uphill/downhill bel pins from ice40 dbClifford Wolf2018-07-242-34/+0
| * Add bbasm target, use as passthru in iCE40 builderDavid Shah2018-07-241-5/+16
| * Add G_ARROW (for now same look as G_LINE)Clifford Wolf2018-07-241-1/+1
| * timing: Model clock to Q timesDavid Shah2018-07-241-0/+15
| * ice40: Trim BRAM constant inputs, reduces routing congestion around BRAMDavid Shah2018-07-241-0/+3
| * ice40: Fix SPRAM and other primitives in corners other than (0, 0)David Shah2018-07-241-1/+1
* | ice40: fixes before reviewSergiusz Bazanski2018-07-245-45/+13
* | ice40: move PLL->IO from pseudo pip to second uphill belSergiusz Bazanski2018-07-243-69/+40
* | ice40: emit list of upbels in chipdbSergiusz Bazanski2018-07-244-16/+22
* | clang-formatSergiusz Bazanski2018-07-243-66/+74
* | ice40: A slightly nicer way to do this.Sergiusz Bazanski2018-07-241-46/+31
* | ice40: Move spliceLUT back to pack.ccSergiusz Bazanski2018-07-243-56/+53
* | ice40: Prevent placement of SB_IOs in IO blocks used by PLL outputsSergiusz Bazanski2018-07-241-0/+24
* | ice40: Refactor PLL/LOCK LUT splicing out into Arch::Sergiusz Bazanski2018-07-244-74/+59
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