Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/pll

9 files changed, 44 insertions, 85 deletions

diff --git a/ice40/arch.cc b/ice40/arch.cc
index 5c632faa..1d7e9546 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -292,23 +292,6 @@ BelRange Arch::getBelsByTile(int x, int y) const
     return br;
 }
 
-BelRange Arch::getBelsAtSameTile(BelId bel) const
-{
-    BelRange br;
-    NPNR_ASSERT(bel != BelId());
-    int x = chip_info->bel_data[bel.index].x;
-    int y = chip_info->bel_data[bel.index].y;
-    int start = bel.index, end = bel.index;
-    while (start >= 0 && chip_info->bel_data[start].x == x && chip_info->bel_data[start].y == y)
-        start--;
-    start++;
-    br.b.cursor = start;
-    while (end < chip_info->num_bels && chip_info->bel_data[end].x == x && chip_info->bel_data[end].y == y)
-        end++;
-    br.e.cursor = end;
-    return br;
-}
-
 PortType Arch::getBelPinType(BelId bel, PortPin pin) const
 {
     NPNR_ASSERT(bel != BelId());
@@ -484,14 +467,6 @@ std::vector<GroupId> Arch::getGroupGroups(GroupId group) const
 
 // -----------------------------------------------------------------------
 
-void Arch::estimatePosition(BelId bel, int &x, int &y, bool &gb) const
-{
-    NPNR_ASSERT(bel != BelId());
-    x = chip_info->bel_data[bel.index].x;
-    y = chip_info->bel_data[bel.index].y;
-    gb = chip_info->bel_data[bel.index].type == TYPE_SB_GB;
-}
-
 delay_t Arch::estimateDelay(WireId src, WireId dst) const
 {
     NPNR_ASSERT(src != WireId());
@@ -735,6 +710,14 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
         } else if (fromPort == id("I2") && toPort == id("COUT")) {
             delay = 230;
             return true;
+        } else if (fromPort == id("CLK") && toPort == id("O")) {
+            delay = 540;
+            return true;
+        }
+    } else if (cell->type == id("ICESTORM_RAM")) {
+        if (fromPort == id("RCLK")) {
+            delay = 2140;
+            return true;
         }
     }
     return false;
@@ -745,6 +728,11 @@ IdString Arch::getPortClock(const CellInfo *cell, IdString port) const
     if (cell->type == id("ICESTORM_LC") && bool_or_default(cell->params, id("DFF_ENABLE"))) {
         if (port != id("LO") && port != id("CIN") && port != id("COUT"))
             return id("CLK");
+    } else if (cell->type == id("ICESTORM_RAM")) {
+        if (port.str(this)[0] == 'R')
+            return id("RCLK");
+        else
+            return id("WCLK");
     }
     return IdString();
 }
@@ -753,6 +741,8 @@ bool Arch::isClockPort(const CellInfo *cell, IdString port) const
 {
     if (cell->type == id("ICESTORM_LC") && port == id("CLK"))
         return true;
+    if (cell->type == id("ICESTORM_RAM") && (port == id("RCLK") || (port == id("WCLK"))))
+        return true;
     return false;
 }
 
diff --git a/ice40/arch.h b/ice40/arch.h
index f0060d48..3aec25a2 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -83,10 +83,6 @@ NPNR_PACKED_STRUCT(struct WireInfoPOD {
     int32_t num_uphill, num_downhill;
     RelPtr<int32_t> pips_uphill, pips_downhill;
 
-    int32_t num_bels_uphill, num_bels_downhill;
-    RelPtr<BelPortPOD> bels_uphill;
-    RelPtr<BelPortPOD> bels_downhill;
-
     int32_t num_bel_pins;
     RelPtr<BelPortPOD> bel_pins;
 
@@ -453,8 +449,6 @@ struct Arch : BaseCtx
 
     bool getBelGlobalBuf(BelId bel) const { return chip_info->bel_data[bel.index].type == TYPE_SB_GB; }
 
-    BelRange getBelsAtSameTile(BelId bel) const NPNR_DEPRECATED;
-
     BelType getBelType(BelId bel) const
     {
         NPNR_ASSERT(bel != BelId());
@@ -685,7 +679,6 @@ struct Arch : BaseCtx
 
     // -------------------------------------------------
 
-    void estimatePosition(BelId bel, int &x, int &y, bool &gb) const NPNR_DEPRECATED;
     delay_t estimateDelay(WireId src, WireId dst) const;
     delay_t getDelayEpsilon() const { return 20; }
     delay_t getRipupDelayPenalty() const { return 200; }
diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index 16cc757e..59e1807d 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -72,7 +72,8 @@ bool Arch::isBelLocationValid(BelId bel) const
 {
     if (getBelType(bel) == TYPE_ICESTORM_LC) {
         std::vector<const CellInfo *> bel_cells;
-        for (auto bel_other : getBelsAtSameTile(bel)) {
+        Loc bel_loc = getBelLocation(bel);
+        for (auto bel_other : getBelsByTile(bel_loc.x, bel_loc.y)) {
             IdString cell_other = getBoundBelCell(bel_other);
             if (cell_other != IdString()) {
                 const CellInfo *ci_other = cells.at(cell_other).get();
@@ -95,8 +96,8 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
         NPNR_ASSERT(getBelType(bel) == TYPE_ICESTORM_LC);
 
         std::vector<const CellInfo *> bel_cells;
-
-        for (auto bel_other : getBelsAtSameTile(bel)) {
+        Loc bel_loc = getBelLocation(bel);
+        for (auto bel_other : getBelsByTile(bel_loc.x, bel_loc.y)) {
             IdString cell_other = getBoundBelCell(bel_other);
             if (cell_other != IdString() && bel_other != bel) {
                 const CellInfo *ci_other = cells.at(cell_other).get();
diff --git a/ice40/arch_pybindings.cc b/ice40/arch_pybindings.cc
index 246d0f57..98164e87 100644
--- a/ice40/arch_pybindings.cc
+++ b/ice40/arch_pybindings.cc
@@ -79,8 +79,6 @@ void arch_wrap_python()
                   conv_to_str<IdString>, conv_from_str<BelId>>::def_wrap(ctx_cls, "getConflictingBelCell");
     fn_wrapper_0a<Context, decltype(&Context::getBels), &Context::getBels, wrap_context<BelRange>>::def_wrap(ctx_cls,
                                                                                                              "getBels");
-    fn_wrapper_1a<Context, decltype(&Context::getBelsAtSameTile), &Context::getBelsAtSameTile, wrap_context<BelRange>,
-                  conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelsAtSameTile");
 
     fn_wrapper_2a<Context, decltype(&Context::getBelPinWire), &Context::getBelPinWire, conv_to_str<WireId>,
                   conv_from_str<BelId>, conv_from_str<PortPin>>::def_wrap(ctx_cls, "getBelPinWire");
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index 63d90b45..108197c1 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -41,8 +41,6 @@ extra_cells = dict()
 extra_cell_config = dict()
 packages = list()
 
-wire_uphill_belports = dict()
-wire_downhill_belports = dict()
 wire_belports = dict()
 
 wire_names = dict()
@@ -453,18 +451,12 @@ for i in range(8):
     add_wire(0, 0, "padin_%d" % i)
 
 def add_bel_input(bel, wire, port):
-    if wire not in wire_downhill_belports:
-        wire_downhill_belports[wire] = set()
-    wire_downhill_belports[wire].add((bel, port))
     if wire not in wire_belports:
         wire_belports[wire] = set()
     wire_belports[wire].add((bel, port))
     bel_wires[bel].append((wire, port, 0))
 
 def add_bel_output(bel, wire, port):
-    if wire not in wire_uphill_belports:
-        wire_uphill_belports[wire] = set()
-    wire_uphill_belports[wire].add((bel, port))
     if wire not in wire_belports:
         wire_belports[wire] = set()
     wire_belports[wire].add((bel, port))
@@ -672,7 +664,7 @@ for tile_xy, tile_type in sorted(tiles.items()):
             add_bel_ec(ec)
 
 for ec in sorted(extra_cells.keys()):
-    if ec[1] == 0 and ec[2] == 0:
+    if ec[1] in (0, dev_width - 1) and ec[2] in (0, dev_height - 1):
         add_bel_ec(ec)
 
 class BinaryBlobAssembler:
@@ -1011,24 +1003,6 @@ for wire in range(num_wires):
         num_downhill = 0
         list_downhill = None
 
-    if wire in wire_uphill_belports:
-        num_bels_uphill = len(wire_uphill_belports[wire])
-        bba.l("wire%d_upbels" % wire, "BelPortPOD")
-        for belport in sorted(wire_uphill_belports[wire]):
-            bba.u32(belport[0], "bel_index")
-            bba.u32(portpins[belport[1]], "port")
-    else:
-        num_bels_uphill = 0
-
-    if wire in wire_downhill_belports:
-        num_bels_downhill = len(wire_downhill_belports[wire])
-        bba.l("wire%d_downbels" % wire, "BelPortPOD")
-        for belport in sorted(wire_downhill_belports[wire]):
-            bba.u32(belport[0], "bel_index")
-            bba.u32(portpins[belport[1]], "port")
-    else:
-        num_bels_downhill = 0
-
     if wire in wire_belports:
         num_bel_pins = len(wire_belports[wire])
         bba.l("wire%d_bels" % wire, "BelPortPOD")
@@ -1047,12 +1021,6 @@ for wire in range(num_wires):
     info["num_downhill"] = num_downhill
     info["list_downhill"] = list_downhill
 
-    info["num_bels_downhill"] = num_bels_downhill
-    info["list_bels_downhill"] = ("wire%d_downbels" % wire) if num_bels_downhill > 0 else None
-
-    info["num_bels_uphill"] = num_bels_uphill
-    info["list_bels_uphill"] = ("wire%d_upbels" % wire) if num_bels_uphill > 0 else None
-
     info["num_bel_pins"] = num_bel_pins
     info["list_bel_pins"] = ("wire%d_bels" % wire) if num_bel_pins > 0 else None
 
@@ -1130,10 +1098,6 @@ for wire, info in enumerate(wireinfo):
     bba.u32(info["num_downhill"], "num_downhill")
     bba.r(info["list_uphill"], "pips_uphill")
     bba.r(info["list_downhill"], "pips_downhill")
-    bba.u32(info["num_bels_uphill"], "num_bels_uphill")
-    bba.u32(info["num_bels_downhill"], "num_bels_downhill")
-    bba.r(info["list_bels_uphill"], "bels_uphill")
-    bba.r(info["list_bels_downhill"], "bels_downhill")
     bba.u32(info["num_bel_pins"], "num_bel_pins")
     bba.r(info["list_bel_pins"], "bel_pins")
     bba.u32(len(wire_segments[wire]), "num_segments")
diff --git a/ice40/family.cmake b/ice40/family.cmake
index 9af06f82..95cdf331 100644
--- a/ice40/family.cmake
+++ b/ice40/family.cmake
@@ -19,13 +19,18 @@ if (MSVC)
     set_source_files_properties(${CMAKE_CURRENT_SOURCE_DIR}/ice40/resources/chipdb.rc PROPERTIES LANGUAGE RC)
     foreach (dev ${devices})
         set(DEV_TXT_DB ${ICEBOX_ROOT}/chipdb-${dev}.txt)
+        set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bba)
         set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bin)
         set(DEV_PORTS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ice40/portpins.inc)
         set(DEV_GFXH ${CMAKE_CURRENT_SOURCE_DIR}/ice40/gfx.h)
-        add_custom_command(OUTPUT ${DEV_CC_DB}
-                COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -b -p ${DEV_PORTS_INC} -g ${DEV_GFXH} ${DEV_TXT_DB} > ${DEV_CC_DB}
+        add_custom_command(OUTPUT ${DEV_CC_BBA_DB}
+                COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -b -p ${DEV_PORTS_INC} -g ${DEV_GFXH} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB}
                 DEPENDS ${DEV_TXT_DB} ${DB_PY}
                 )
+        add_custom_command(OUTPUT ${DEV_CC_DB}
+                COMMAND bbasm < ${DEV_CC_BBA_DB} > ${DEV_CC_DB}
+                DEPENDS bbasm ${DEV_CC_BBA_DB}
+        )
         target_sources(ice40_chipdb PRIVATE ${DEV_CC_DB})
         set_source_files_properties(${DEV_CC_DB} PROPERTIES HEADER_FILE_ONLY TRUE)
         foreach (target ${family_targets})
@@ -36,14 +41,20 @@ else()
     target_compile_options(ice40_chipdb PRIVATE -g0 -O0 -w)
     foreach (dev ${devices})
         set(DEV_TXT_DB ${ICEBOX_ROOT}/chipdb-${dev}.txt)
+        set(DEV_CC_BBA_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.bba)
         set(DEV_CC_DB ${CMAKE_CURRENT_SOURCE_DIR}/ice40/chipdbs/chipdb-${dev}.cc)
         set(DEV_PORTS_INC ${CMAKE_CURRENT_SOURCE_DIR}/ice40/portpins.inc)
         set(DEV_GFXH ${CMAKE_CURRENT_SOURCE_DIR}/ice40/gfx.h)
+        add_custom_command(OUTPUT ${DEV_CC_BBA_DB}
+                COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -c -p ${DEV_PORTS_INC} -g ${DEV_GFXH} ${DEV_TXT_DB} > ${DEV_CC_BBA_DB}.new
+                COMMAND mv ${DEV_CC_BBA_DB}.new ${DEV_CC_BBA_DB}
+                DEPENDS ${DEV_TXT_DB} ${DB_PY}
+        )
         add_custom_command(OUTPUT ${DEV_CC_DB}
-                COMMAND ${PYTHON_EXECUTABLE} ${DB_PY} -c -p ${DEV_PORTS_INC} -g ${DEV_GFXH} ${DEV_TXT_DB} > ${DEV_CC_DB}.new
+                COMMAND bbasm < ${DEV_CC_BBA_DB} > ${DEV_CC_DB}.new
                 COMMAND mv ${DEV_CC_DB}.new ${DEV_CC_DB}
-                DEPENDS ${DEV_TXT_DB} ${DB_PY}
-                )
+                DEPENDS bbasm ${DEV_CC_BBA_DB}
+        )
         target_sources(ice40_chipdb PRIVATE ${DEV_CC_DB})
         foreach (target ${family_targets})
             target_sources(${target} PRIVATE $<TARGET_OBJECTS:ice40_chipdb>)
diff --git a/ice40/gfx.cc b/ice40/gfx.cc
index f6ed789f..1b01cbd8 100644
--- a/ice40/gfx.cc
+++ b/ice40/gfx.cc
@@ -647,7 +647,7 @@ void pipGfx(std::vector<GraphicElement> &g, int x, int y, float x1, float y1, fl
     float ty = 0.5 * (y1 + y2);
 
     GraphicElement el;
-    el.type = GraphicElement::G_LINE;
+    el.type = GraphicElement::G_ARROW;
     el.style = style;
 
     if (fabsf(x1 - swx1) < 0.001 && fabsf(x2 - swx1) < 0.001) {
diff --git a/ice40/pack.cc b/ice40/pack.cc
index 03b33190..b1e7380e 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -312,6 +312,10 @@ static void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constne
                        (user.port != ctx->id("CLK") &&
                         ((constval && user.port == ctx->id("CE")) || (!constval && user.port != ctx->id("CE"))))) {
                 uc->ports[user.port].net = nullptr;
+            } else if (is_ram(ctx, uc) && !constval && user.port != ctx->id("RCLK") && user.port != ctx->id("RCLKN") &&
+                       user.port != ctx->id("WCLK") && user.port != ctx->id("WCLKN") && user.port != ctx->id("RCLKE") &&
+                       user.port != ctx->id("WCLKE")) {
+                uc->ports[user.port].net = nullptr;
             } else {
                 uc->ports[user.port].net = constnet;
                 constnet->users.push_back(user);
diff --git a/ice40/place_legaliser.cc b/ice40/place_legaliser.cc
index 2aefb839..ebc2b865 100644
--- a/ice40/place_legaliser.cc
+++ b/ice40/place_legaliser.cc
@@ -75,11 +75,9 @@ static void get_chain_midpoint(const Context *ctx, const CellChain &chain, float
     for (auto cell : chain.cells) {
         if (cell->bel == BelId())
             continue;
-        int bel_x, bel_y;
-        bool bel_gb;
-        ctx->estimatePosition(cell->bel, bel_x, bel_y, bel_gb);
-        total_x += bel_x;
-        total_y += bel_y;
+        Loc bel_loc = ctx->getBelLocation(cell->bel);
+        total_x += bel_loc.x;
+        total_y += bel_loc.y;
         N++;
     }
     NPNR_ASSERT(N > 0);