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* ice40: Creating packer testsDavid Shah2018-06-124-0/+233
* Implement the placement validity checkerDavid Shah2018-06-121-1/+1
* ice40: Adding a placement validity checkerDavid Shah2018-06-125-6/+148
* ice40: Pack constants to LCsDavid Shah2018-06-124-8/+35
* ice40: Debugging the packerDavid Shah2018-06-124-3/+36
* ice40: Start working on a packer, currently not testedDavid Shah2018-06-124-0/+124
* ice40: Adding cell utilities for packingDavid Shah2018-06-122-0/+164
* ice40: Optimising chipdb buildsDavid Shah2018-06-121-0/+1
* Add "nextpnr.h"Clifford Wolf2018-06-116-10/+9
* Remove pool, dict, vector namespace aliasesClifford Wolf2018-06-113-26/+27
* Add conflicting=false argument to bind gettersClifford Wolf2018-06-111-3/+4
* Fixed portability issue, now it works on msys2 windows build as wellMiodrag Milanovic2018-06-111-2/+3
* Pass design to gui, display chip nameMiodrag Milanovic2018-06-103-1/+32
* Improving 5k supportDavid Shah2018-06-104-22/+59
* Fix iCE40 routing graphClifford Wolf2018-06-102-28/+1
* Add support for iCE40 global buffers (currently only for 1k devices)Clifford Wolf2018-06-108-124/+198
* Debugging on icebreakerDavid Shah2018-06-104-11/+217
* Add blinky post-synthesis testbenchClifford Wolf2018-06-103-5/+26
* Fix ice40 pip/switch locked performance issueClifford Wolf2018-06-103-16/+9
* ice40: Set config bits for unused IODavid Shah2018-06-101-1/+19
* ice40: Fix techmapDavid Shah2018-06-101-1/+1
* ice40: Add IO config to bitstreamDavid Shah2018-06-103-17/+93
* ice40: Write logic cell config to bitstreamDavid Shah2018-06-103-7/+60
* ice40: Lock out mutually exclusive pipsDavid Shah2018-06-102-2/+13
* ice40: Start adding routing to asc outputDavid Shah2018-06-101-0/+34
* ice40: Writing an empty ASC fileDavid Shah2018-06-105-1/+138
* ice40: Adding non-routing config bits to databaseDavid Shah2018-06-102-10/+63
* ice40: Add switch data to databaseDavid Shah2018-06-102-6/+95
* Renamed LOC attribute to BEL, fix ice40 IO bel namesClifford Wolf2018-06-092-9/+9
* Adding basic placement constraintsDavid Shah2018-06-091-3/+77
* Getting rid of .nil() methods, compare with zero- and default-constructed obj...Clifford Wolf2018-06-094-48/+36
* Add very basic routerClifford Wolf2018-06-095-35/+150
* python: Fixing builds as importable moduleDavid Shah2018-06-081-0/+5
* Reformat remaining filesDavid Shah2018-06-081-1/+0
* Applied clang-format to my own contributionsZipCPU2018-06-072-10/+14
* Set the default log to stdoutZipCPU2018-06-072-2/+17
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| * Moved placer definitions to place.h, main automatically runs placer nowZipCPU2018-06-071-3/+2
| * Initial (random) placer capabilityZipCPU2018-06-071-1/+12
| * Preliminary placer changes to mainZipCPU2018-06-071-0/+7
* | ice40: More Python bindings and examplesDavid Shah2018-06-072-1/+17
* | ice40: Refactor PortPin and add Python bindingDavid Shah2018-06-075-318/+126
* | Connected the log file facility to stderrZipCPU2018-06-071-0/+3
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* cmake: Add HX1K-only builds supportDavid Shah2018-06-071-1/+9
* Reformat Python bindings and ice40 mainDavid Shah2018-06-072-225/+230
* Fixing file->run renamingDavid Shah2018-06-071-1/+1
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrDavid Shah2018-06-073-813/+819
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| * clang-format for design and chip codebaseClifford Wolf2018-06-072-813/+817
| * Fix clang-format include order issuesClifford Wolf2018-06-071-0/+2
* | Merge branch 'python'David Shah2018-06-071-1/+2
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| * Global design object workingDavid Shah2018-06-071-1/+1
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