Remove pool, dict, vector namespace aliases

Signed-off-by: Clifford Wolf <clifford@clifford.at>

3 files changed, 27 insertions, 26 deletions

diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index a6ab060f..944e80c2 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -49,7 +49,8 @@ std::tuple<int8_t, int8_t, int8_t> get_ieren(const BitstreamInfoPOD &bi,
     return std::make_tuple(-1, -1, -1);
 };
 
-void set_config(const TileInfoPOD &ti, vector<vector<int8_t>> &tile_cfg,
+void set_config(const TileInfoPOD &ti,
+                std::vector<std::vector<int8_t>> &tile_cfg,
                 const std::string &name, bool value, int index = -1)
 {
     const ConfigEntryPOD &cfg = find_config(ti, name);
@@ -78,7 +79,7 @@ void write_asc(const Design &design, std::ostream &out)
             TileType tile = tile_at(chip, x, y);
             int rows = bi.tiles_nonrouting[tile].rows;
             int cols = bi.tiles_nonrouting[tile].cols;
-            config.at(y).at(x).resize(rows, vector<int8_t>(cols));
+            config.at(y).at(x).resize(rows, std::vector<int8_t>(cols));
         }
     }
     out << ".comment from next-pnr" << std::endl;
@@ -137,7 +138,7 @@ void write_asc(const Design &design, std::ostream &out)
             bool async_sr = std::stoi(cell.second->params["ASYNC_SR"]);
             bool set_noreset = std::stoi(cell.second->params["SET_NORESET"]);
             bool carry_enable = std::stoi(cell.second->params["CARRY_ENABLE"]);
-            vector<bool> lc(20, false);
+            std::vector<bool> lc(20, false);
             // From arachne-pnr
             static std::vector<int> lut_perm = {
                     4, 14, 15, 5, 6, 16, 17, 7, 3, 13, 12, 2, 1, 11, 10, 0,
diff --git a/ice40/chip.cc b/ice40/chip.cc
index e6116287..5f6560c5 100644
--- a/ice40/chip.cc
+++ b/ice40/chip.cc
@@ -231,9 +231,9 @@ void Chip::getPipPosition(PipId pip, float &x, float &y) const
     y = chip_info.pip_data[pip.index].y;
 }
 
-vector<GraphicElement> Chip::getBelGraphics(BelId bel) const
+std::vector<GraphicElement> Chip::getBelGraphics(BelId bel) const
 {
-    vector<GraphicElement> ret;
+    std::vector<GraphicElement> ret;
 
     auto bel_type = getBelType(bel);
 
@@ -297,23 +297,23 @@ vector<GraphicElement> Chip::getBelGraphics(BelId bel) const
     return ret;
 }
 
-vector<GraphicElement> Chip::getWireGraphics(WireId wire) const
+std::vector<GraphicElement> Chip::getWireGraphics(WireId wire) const
 {
-    vector<GraphicElement> ret;
+    std::vector<GraphicElement> ret;
     // FIXME
     return ret;
 }
 
-vector<GraphicElement> Chip::getPipGraphics(PipId pip) const
+std::vector<GraphicElement> Chip::getPipGraphics(PipId pip) const
 {
-    vector<GraphicElement> ret;
+    std::vector<GraphicElement> ret;
     // FIXME
     return ret;
 }
 
-vector<GraphicElement> Chip::getFrameGraphics() const
+std::vector<GraphicElement> Chip::getFrameGraphics() const
 {
-    vector<GraphicElement> ret;
+    std::vector<GraphicElement> ret;
 
     for (int x = 0; x <= chip_info.width; x++)
         for (int y = 0; y <= chip_info.height; y++) {
diff --git a/ice40/chip.h b/ice40/chip.h
index b7492d2f..3ab3f3d2 100644
--- a/ice40/chip.h
+++ b/ice40/chip.h
@@ -406,14 +406,14 @@ struct Chip
 {
     ChipInfoPOD chip_info;
 
-    mutable dict<IdString, int> bel_by_name;
-    mutable dict<IdString, int> wire_by_name;
-    mutable dict<IdString, int> pip_by_name;
-
-    vector<IdString> bel_to_cell;
-    vector<IdString> wire_to_net;
-    vector<IdString> pip_to_net;
-    vector<bool> switches_locked;
+    mutable std::unordered_map<IdString, int> bel_by_name;
+    mutable std::unordered_map<IdString, int> wire_by_name;
+    mutable std::unordered_map<IdString, int> pip_by_name;
+
+    std::vector<IdString> bel_to_cell;
+    std::vector<IdString> wire_to_net;
+    std::vector<IdString> pip_to_net;
+    std::vector<bool> switches_locked;
     Chip(ChipArgs args);
 
     ChipArgs args;
@@ -449,7 +449,7 @@ struct Chip
         return bel_to_cell[bel.index] == IdString();
     }
 
-    IdString getBelCell(BelId bel, bool conflicting=false) const
+    IdString getBelCell(BelId bel, bool conflicting = false) const
     {
         assert(bel != BelId());
         return bel_to_cell[bel.index];
@@ -539,7 +539,7 @@ struct Chip
         return wire_to_net[wire.index] == IdString();
     }
 
-    IdString getWireNet(WireId wire, bool conflicting=false) const
+    IdString getWireNet(WireId wire, bool conflicting = false) const
     {
         assert(wire != WireId());
         return wire_to_net[wire.index];
@@ -596,7 +596,7 @@ struct Chip
         return !switches_locked[chip_info.pip_data[pip.index].switch_index];
     }
 
-    IdString getPipNet(PipId pip, bool conflicting=false) const
+    IdString getPipNet(PipId pip, bool conflicting = false) const
     {
         assert(pip != PipId());
         return pip_to_net[pip.index];
@@ -669,10 +669,10 @@ struct Chip
     void getWirePosition(WireId wire, float &x, float &y) const;
     void getPipPosition(PipId pip, float &x, float &y) const;
 
-    vector<GraphicElement> getBelGraphics(BelId bel) const;
-    vector<GraphicElement> getWireGraphics(WireId wire) const;
-    vector<GraphicElement> getPipGraphics(PipId pip) const;
-    vector<GraphicElement> getFrameGraphics() const;
+    std::vector<GraphicElement> getBelGraphics(BelId bel) const;
+    std::vector<GraphicElement> getWireGraphics(WireId wire) const;
+    std::vector<GraphicElement> getPipGraphics(PipId pip) const;
+    std::vector<GraphicElement> getFrameGraphics() const;
 };
 
 #endif