Commit message (Collapse) | Author | Age | Files | Lines | |
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* | enable lading of jsons and setting up context | Miodrag Milanovic | 2019-06-14 | 1 | -0/+2 |
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* | Use flags for each step | Miodrag Milanovic | 2019-06-14 | 2 | -3/+3 |
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* | restore arch info for ecp5 | Miodrag Milanovic | 2019-06-14 | 1 | -0/+3 |
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* | restore context from json | Miodrag Milanovic | 2019-06-14 | 1 | -3/+43 |
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* | Load properties from json and propagate to context create | Miodrag Milanovic | 2019-06-13 | 1 | -2/+2 |
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* | Save settings that we saved in project | Miodrag Milanovic | 2019-06-13 | 1 | -1/+1 |
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* | Remove concept of project and code connected | Miodrag Milanovic | 2019-06-13 | 1 | -76/+0 |
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* | Use properties for settings and save in json | Miodrag Milanovic | 2019-06-12 | 1 | -1/+1 |
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* | Save top level attrs and store current step | Miodrag Milanovic | 2019-06-07 | 2 | -0/+3 |
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* | Add vcc and gnd nets and cells only if needed | Miodrag Milanovic | 2019-06-07 | 1 | -5/+20 |
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* | Cleanup | Miodrag Milanovic | 2019-06-07 | 2 | -13/+0 |
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* | WIP saving/loading attributes | Miodrag Milanovic | 2019-06-07 | 3 | -4/+23 |
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* | Revert "Do not add VCC if not used, loading json works" | Miodrag Milanovic | 2019-06-02 | 1 | -6/+5 |
| | | | | This reverts commit f1b3a14bc23ccee6acaf6bbe27827523dc13c111. | ||||
* | Added support for attributes/properties types | Miodrag Milanovic | 2019-06-01 | 1 | -1/+1 |
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* | Do not add VCC if not used, loading json works | Miodrag Milanovic | 2019-05-31 | 1 | -5/+6 |
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* | ice40: Add support for HFOSC trimming | Sylvain Munaut | 2019-05-13 | 1 | -0/+5 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | Merge pull request #270 from smunaut/sb_io_conflict | David Shah | 2019-04-17 | 2 | -2/+38 |
|\ | | | | | SB IO conflict checks | ||||
| * | ice40: Check for SB_IO shared wires conflicts in isValidBelForCell | Sylvain Munaut | 2019-04-17 | 1 | -0/+36 |
| | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| * | ice40: In assignCellInfo get PIN_TYPE/NEG_TRIGGER from params and not attrs | Sylvain Munaut | 2019-04-17 | 1 | -2/+2 |
| | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | | ice40: Only create padin gbuf for PLLs if global output actually used | Sylvain Munaut | 2019-04-17 | 1 | -11/+38 |
| | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | | ice40: Take placed SB_GBs into account when placing PLLs | Sylvain Munaut | 2019-04-16 | 1 | -9/+55 |
|/ | | | | | | | | | | | | | | | | Because the PLLs drive global networks, we need to account for already existing and placed SB_GBs when trying to place/pack them. Theses can be user instanciated SB_GBs with BEL attribute, or SB_GB_IOs that got converted during the IO packing. This patch assumes that: - If a PLL is used the output A global network is always used, even if there is no connection to the global output pin - If a PLL with a singe output is used, then the B output global network is still free to be used by whatever. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40/pack: During IO packing, remove any unused input connection | Sylvain Munaut | 2019-04-11 | 1 | -0/+13 |
| | | | | | | | | | This is mostly for the benefit of PLL placement because the D_IN_x ports are used for other purposes when PLL is enabled so we need to make sure nothing is connected there already. (even an unused net is too much) Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Don't constrain to a PLL bel that has already been used | David Shah | 2019-04-01 | 1 | -0/+2 |
| | | | | | | Fixes #258 Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: Add support for SB_I2C and SB_SPI | Sylvain Munaut | 2019-03-25 | 5 | -1/+112 |
| | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | Add --placer option and refactor placer selection | David Shah | 2019-03-24 | 3 | -6/+16 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | HeAP: Add PlacerHeapCfg | David Shah | 2019-03-22 | 1 | -1/+3 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | HeAP: Make HeAP placer optional | David Shah | 2019-03-22 | 2 | -5/+11 |
| | | | | | | | | | | | | | A CMake option 'BUILD_HEAP' (default on) configures building of the HeAP placer and the associated Eigen3 dependency. Default for the iCE40 is SA placer, with --heap-placer to use HeAP Default for the ECP5 is HeAP placer, as SA placer can take 1hr+ for large ECP5 designs and HeAP tends to give better QoR. --sa-placer can be used to use SA instead, and auto-fallback to SA if HeAP not built. Signed-off-by: David Shah <dave@ds0.me> | ||||
* | HeAP: Add TAUCS wrapper and integration | David Shah | 2019-03-22 | 1 | -2/+4 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: Add examples folder including floorplan example | David Shah | 2019-03-22 | 11 | -0/+42 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Add Python helper functions for floorplanning | David Shah | 2019-03-22 | 1 | -0/+7 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: Fix u4k in external chipdb mode. | Marcin Kościelnicki | 2019-03-19 | 1 | -3/+3 |
| | | | | Signed-off-by: Marcin Kościelnicki <marcin@symbioticeda.com> | ||||
* | ice40: u4k merge fix | David Shah | 2019-02-25 | 1 | -0/+2 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Merge pull request #239 from YosysHQ/dsp_casc_dummy_wires | David Shah | 2019-02-25 | 2 | -0/+24 |
|\ | | | | | ice40: Add DSP SIGNEXTIN/OUT and ACCUMCI/O ports | ||||
| * | ice40: Add DSP SIGNEXTIN/OUT and ACCUMCI/O ports | David Shah | 2019-02-21 | 2 | -0/+24 |
| | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | | ice40: support u4k | Simon Schubert | 2019-02-23 | 13 | -13/+57 |
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* | ice40: Fix timing class of 'padin' GB outputs | David Shah | 2019-02-20 | 1 | -1/+1 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | Merge branch 'master' into mmaped_chipdb | Miodrag Milanović | 2019-02-12 | 1 | -1/+8 |
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| * | ice40: PLLs can't conflict with themselves | David Shah | 2019-02-09 | 1 | -0/+2 |
| | | | | | | | | | | | | Fixes error building testcase from #145 Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | ice40: Don't create PLLOUT_B buffer for single-output PLL variants | David Shah | 2019-02-09 | 1 | -1/+6 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | Fix according to comments on PR | Miodrag Milanovic | 2019-02-10 | 1 | -1/+1 |
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* | | Load chipdb from filesystem as option | Miodrag Milanovic | 2019-02-09 | 3 | -83/+114 |
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* | Merge pull request #220 from YosysHQ/coi3 | Eddie Hung | 2019-01-29 | 1 | -6/+9 |
|\ | | | | | ice40: Add budget override for CO->I3 path | ||||
| * | [ice40] Refactor Arch::getBudgetOverride() | Eddie Hung | 2019-01-29 | 1 | -29/+9 |
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| * | ice40: Add budget override for CO->I3 path | David Shah | 2019-01-27 | 1 | -0/+23 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | timing: Path related fixes | David Shah | 2019-01-27 | 2 | -6/+33 |
|/ | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Merge pull request #211 from smunaut/ice40_ram_attrs | David Shah | 2019-01-21 | 1 | -0/+4 |
|\ | | | | | ice40/pack: Copy attributes to packed cell | ||||
| * | ice40/pack: Copy attributes to packed RAM cells | Sylvain Munaut | 2019-01-19 | 1 | -0/+4 |
| | | | | | | | | | | | | | | Useful to allow manual placement of SPRAM/EBR using BEL attribute for instance Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | | ice40: Add error message if a selected site is not Global Buffer capable | Sylvain Munaut | 2019-01-18 | 1 | -0/+4 |
|/ | | | | | | ... rather than assert()-out during the call to getWireBelPins() call Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | ice40: Add timing data for all IO modes | David Shah | 2019-01-07 | 2 | -3/+67 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ice40: Improve handling of unconstrained IO | David Shah | 2018-12-26 | 3 | -3/+23 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> |