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authorMiodrag Milanović <mmicko@gmail.com>2019-02-12 18:53:20 +0100
committerGitHub <noreply@github.com>2019-02-12 18:53:20 +0100
commitc52202233a3f1b06d68314dccc7cc12c8fdfe5f2 (patch)
tree5930a48f9052d020d1b1eacd4cfebcc266737ffe /ice40
parent8b0af0e48d22779b5f2e047541e9e037375cb4cd (diff)
parentd24d85a6e4f82845cab51252308a2904db37c302 (diff)
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Merge branch 'master' into mmaped_chipdb
Diffstat (limited to 'ice40')
-rw-r--r--ice40/pack.cc9
1 files changed, 8 insertions, 1 deletions
diff --git a/ice40/pack.cc b/ice40/pack.cc
index a86083b6..c22c4e8c 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -770,6 +770,8 @@ static void place_plls(Context *ctx)
io_cell->name.c_str(ctx));
if (pll_used_bels.count(found_bel)) {
CellInfo *conflict_cell = pll_used_bels.at(found_bel);
+ if (conflict_cell == ci)
+ continue;
log_error("PLL '%s' PACKAGEPIN forces it to BEL %s but BEL is already assigned to PLL '%s'\n",
ci->name.c_str(ctx), ctx->getBelName(found_bel).c_str(ctx), conflict_cell->name.c_str(ctx));
}
@@ -1063,7 +1065,12 @@ static void pack_special(Context *ctx)
create_ice_cell(ctx, ctx->id("ICESTORM_PLL"), ci->name.str(ctx) + "_PLL");
packed->attrs[ctx->id("TYPE")] = ci->type.str(ctx);
packed_cells.insert(ci->name);
-
+ if (!is_sb_pll40_dual(ctx, ci)) {
+ // Remove second output, so a buffer isn't created for it, for these
+ // cell types with only one output
+ packed->ports.erase(ctx->id("PLLOUT_B"));
+ packed->ports.erase(ctx->id("PLLOUT_B_GLOBAL"));
+ }
for (auto attr : ci->attrs)
packed->attrs[attr.first] = attr.second;
for (auto param : ci->params)