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* Add ice40/benchmark/report.ipynbClifford Wolf2018-07-251-0/+69
* More minor ice40 benchmark improvementsClifford Wolf2018-07-252-2/+7
* ice40: Tweaking picorv32_benchmark.pyDavid Shah2018-07-251-2/+1
* Minor improvements in iCE40 benchmark scriptsClifford Wolf2018-07-252-2/+7
* Add ice40/benchmark/Clifford Wolf2018-07-257-0/+4136
* Merge branch 'bba' into 'master'Clifford Wolf2018-07-252-277/+42
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| * proper options for linux buildMiodrag Milanovic2018-07-251-1/+1
| * Use bbasm to create iCE40 chipdbClifford Wolf2018-07-242-277/+42
* | ice40: after reviewSergiusz Bazanski2018-07-252-3/+3
* | ice40: check PLL PACKAGEPIN drives only PLL, cosmeticsSergiusz Bazanski2018-07-251-4/+7
* | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/pll-padsSergiusz Bazanski2018-07-251-0/+43
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| * | Add a simple 8x benchmark scriptDavid Shah2018-07-251-0/+43
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* | clang-formatSergiusz Bazanski2018-07-251-7/+7
* | ice40: support PLL40_*_PAD, fix pass-through LUT for LOCKSergiusz Bazanski2018-07-253-7/+81
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* ice40: after reviewSergiusz Bazanski2018-07-241-1/+0
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/pllSergiusz Bazanski2018-07-249-85/+44
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| * Remove implementations of deprecated APIsDavid Shah2018-07-243-30/+0
| * ice40: Remove use of deprecated APIsDavid Shah2018-07-243-10/+10
| * Remove uphill/downhill bel pins from ice40 dbClifford Wolf2018-07-242-34/+0
| * Add bbasm target, use as passthru in iCE40 builderDavid Shah2018-07-241-5/+16
| * Add G_ARROW (for now same look as G_LINE)Clifford Wolf2018-07-241-1/+1
| * timing: Model clock to Q timesDavid Shah2018-07-241-0/+15
| * ice40: Trim BRAM constant inputs, reduces routing congestion around BRAMDavid Shah2018-07-241-0/+3
| * ice40: Fix SPRAM and other primitives in corners other than (0, 0)David Shah2018-07-241-1/+1
* | ice40: fixes before reviewSergiusz Bazanski2018-07-245-45/+13
* | ice40: move PLL->IO from pseudo pip to second uphill belSergiusz Bazanski2018-07-243-69/+40
* | ice40: emit list of upbels in chipdbSergiusz Bazanski2018-07-244-16/+22
* | clang-formatSergiusz Bazanski2018-07-243-66/+74
* | ice40: A slightly nicer way to do this.Sergiusz Bazanski2018-07-241-46/+31
* | ice40: Move spliceLUT back to pack.ccSergiusz Bazanski2018-07-243-56/+53
* | ice40: Prevent placement of SB_IOs in IO blocks used by PLL outputsSergiusz Bazanski2018-07-241-0/+24
* | ice40: Refactor PLL/LOCK LUT splicing out into Arch::Sergiusz Bazanski2018-07-244-74/+59
* | ice40: Emit feed-through LUTs for PLL/LOCKSergiusz Bazanski2018-07-242-2/+159
* | ice40: Fail early on SB_PLL40_*_PAD cellsSergiusz Bazanski2018-07-242-0/+14
* | ice40: Implement emitting PLLsSergiusz Bazanski2018-07-249-16/+269
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* Add Context::archcheck() and "nextpnr-ice40 --test"Clifford Wolf2018-07-232-40/+60
* Remove getBelsByType() APIClifford Wolf2018-07-231-14/+0
* clangformatDavid Shah2018-07-231-2/+3
* Add getGridDimX(), getGridDimY(), getTileDimZ() APIClifford Wolf2018-07-231-0/+6
* Bugfix in iCE40 chipdb.pyClifford Wolf2018-07-231-3/+0
* Move to new API and remove deprecatedMiodrag Milanovic2018-07-223-63/+40
* Add Arch::getBelPins() to generic and iCE40 archsClifford Wolf2018-07-222-0/+17
* Add Arch::getBelPinType() and Arch::getWireBelPins() in iCE40 archClifford Wolf2018-07-223-4/+57
* Rename getWireBelPin to getBelPinWireClifford Wolf2018-07-226-18/+18
* clangformatClifford Wolf2018-07-223-8/+4
* Merge branch 'q3k/lock-2-electric-boogaloo' into 'master'Clifford Wolf2018-07-212-4/+12
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| * Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-elec...Sergiusz Bazanski2018-07-219-543/+904
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| * | Re-enable drawing Pips.Sergiusz Bazanski2018-07-201-3/+3
| * | clang-formatSergiusz Bazanski2018-07-201-1/+1
| * | Nuke IdStringDBSergiusz Bazanski2018-07-201-1/+1
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