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* ice40: Implement IdStringList for all arch object namesD. Shah2021-02-025-57/+88
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* refactor: Replace getXName().c_str(ctx) with ctx->nameOfXD. Shah2021-02-022-6/+5
| | | | | | This makes the ongoing migration to IdStringList easier. Signed-off-by: D. Shah <dave@ds0.me>
* arch: Add getNameDelimiter API for string listsD. Shah2021-02-021-0/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Run "make clangformat".Keith Rothman2021-02-024-28/+21
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add pybindings for new APIs.Keith Rothman2021-02-022-0/+14
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Rename Partition -> BelBucket.Keith Rothman2021-02-023-29/+29
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add Partition APIs to ice40, nexus, gowin archs.Keith Rothman2021-02-023-0/+78
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial refactoring of placer API.Keith Rothman2021-02-021-0/+5
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Seperate PipRange types in pybindings_shared.Keith Rothman2021-02-011-0/+4
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* cleanup: Spelling fixesD. Shah2021-01-281-1/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* cleanup: Remove dead/unused codeD. Shah2021-01-281-32/+0
| | | | | | | Note that some '#if 0' code that might still be useful for debugging in the future has been retained. Signed-off-by: D. Shah <dave@ds0.me>
* Move RelPtr/RelSlice out of arches into commonD. Shah2021-01-271-42/+1
| | | | | | | The bba approach seems widely used enough that it's reasonable for this to become part of common code. Signed-off-by: D. Shah <dave@ds0.me>
* ice40: Switch from RelPtr to RelSliceD. Shah2021-01-276-149/+137
| | | | | | | | | | This replaces RelPtrs and a separate length field with a Rust-style slice containing both a pointer and a length; with bounds checking always enforced. Thus iterating over these structures is both cleaner and safer. Signed-off-by: D. Shah <dave@ds0.me>
* ice40: Nicer error for unconstrained SB_GB_IODavid Shah2020-12-271-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Use std::string::find(char c) when searching for a single character.Tim Callahan2020-12-161-1/+1
| | | | Signed-off-by: Tim Callahan <tcal@google.com>
* ice40: Clarify feedback paths in PLL constraints codeDavid Shah2020-12-031-3/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Derive PLL timing constraintsDavid Shah2020-12-031-31/+138
| | | | Signed-off-by: David Shah <dave@ds0.me>
* RelPtr: remove copy constructor and copy assignmentDavid Shah2020-11-131-0/+3
| | | | | | | These operations are meaningless for a data structure that references another structure relative to its location. Signed-off-by: David Shah <dave@ds0.me>
* ice40/pack/SB_PLL: Force fixed value to 4'b1111 if dynamic delay is usedSylvain Munaut2020-11-101-7/+9
| | | | | | | | It's been confirmed that : (1) this is required by the hardware (2) icecube will force that field to 4'b1111 in fixed mode Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Remove wire alias APIDavid Shah2020-10-151-9/+0
| | | | | | It has not actually been implemented in any router for over 2.5 years and causes nothing more than confusion. It can always be added back if it forms part of a future solution; possibly as part of a more general database structure rethink. Signed-off-by: David Shah <dave@ds0.me>
* CMake: fix Windows-ism in status messagewhitequark2020-08-261-1/+1
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* Fix MESSAGE indicating where externally-built .bbas live.William D. Jones2020-08-221-1/+1
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* Initial conversion to pybind11Miodrag Milanovic2020-07-231-19/+17
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* ice40: If IO is used by SB_GB_IO, can't use it for PLLSylvain Munaut2020-07-091-1/+2
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Fixes for new part typesMiodrag Milanovic2020-07-085-16/+43
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* Use proper names in GUIMiodrag Milanovic2020-07-081-12/+12
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* Support rest of partsMiodrag Milanovic2020-07-083-13/+58
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* Missed adding optionMiodrag Milanovic2020-07-081-0/+2
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* Adding LP4K as wellMiodrag Milanovic2020-07-083-3/+16
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* Support 4K parts directlyMiodrag Milanovic2020-07-083-5/+33
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* Merge pull request #463 from YosysHQ/fix-archcheckDavid Shah2020-07-022-2/+6
|\ | | | | Fix arch checks, and add these to CI
| * ice40: Fix getBelsByTileDavid Shah2020-06-292-2/+6
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | CMake: fix path checks in chipdb build scripts.whitequark2020-07-011-1/+1
|/ | | | | | | `if(NOT DEFINED)` is not appropriate since a variable that contains `-NOTFOUND` still counts as `DEFINED`. This can cause issues if configuration fails, writes `-NOTFOUND` to the cache, and is then restarted.
* Make python bindings consistentMiodrag Milanovic2020-06-272-2/+4
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* Fix clangformat and execute itMiodrag Milanovic2020-06-271-6/+4
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* Update git ignore locationsMiodrag Milanovic2020-06-271-1/+1
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* Simplify and improve chipdb embedding/loading.whitequark2020-06-268-152/+62
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* CMake: require at least version 3.5 (Ubuntu 16.04).whitequark2020-06-251-1/+1
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* CMake: rewrite chipdb handling from ground up.whitequark2020-06-255-127/+145
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* ice40: Add fallback behavior for Extra Cell config bits vectorsSylvain Munaut2020-06-021-1/+11
| | | | | | | This helps make new nextpnr compatible with old chipdbs when a parameters goes from single bit to multi bit. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add support for the 2nd bit of SHIFTREG_DIV_MODESylvain Munaut2020-06-021-1/+1
| | | | | | This requires the matching chipdb update from icestorm project ! Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Merge pull request #447 from whitequark/wasiDavid Shah2020-05-241-2/+2
|\ | | | | Port nextpnr-{ice40,ecp5} to WASI
| * Port nextpnr-{ice40,ecp5} to WASI.whitequark2020-05-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This involves very few changes, all typical to WASM ports: * WASM doesn't currently support threads or atomics so those are disabled. * WASM doesn't currently support exceptions so the exception machinery is stubbed out. * WASM doesn't (and can't) have mmap(), so an emulation library is used. That library currently doesn't support MAP_SHARED flags, so MAP_PRIVATE is used instead. There is also an update to bring ECP5 bbasm CMake rules to parity with iCE40 ones, since although it is possible to embed chipdb into nextpnr on WASM, a 200 MB WASM file has very few practical uses. The README is not updated and there is no included toolchain file because at the moment it's not possible to build nextpnr with upstream boost and wasi-libc. Boost requires a patch (merged, will be available in boost 1.74.0), wasi-libc requires a few unmerged patches.
* | Fix spelling of 'unsupported'Nathaniel Graff2020-05-131-4/+4
|/ | | | Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
* ice40: Derive oscillator frequency constraintsDavid Shah2020-03-291-0/+40
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Fix output register timing analysis for registered output enableSylvain Munaut2020-03-291-1/+1
| | | | | | | Wrong bits were being tested. [5:4] is what's controlling the output enable path. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Always copy DFF attrs to LCDavid Shah2020-03-191-0/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #400 from YosysHQ/dave/tri-fixesDavid Shah2020-03-101-1/+18
|\ | | | | Improve handling of unused inout port bits
| * Improve handling of unused inout port bitsDavid Shah2020-02-251-1/+18
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | build: Default the ECP5 and iCE40 roots to the install prefixSylvain Munaut2020-03-031-1/+1
|/ | | | | | | | | If the user specifies a custom install prefix, chances are icestrom/trellis are also in that prefix rather than the hardcoded /usr/local Fixes #351 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
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