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| author | D. Shah <dave@ds0.me> | 2021-01-28 15:19:06 +0000 |
|---|---|---|
| committer | D. Shah <dave@ds0.me> | 2021-01-28 15:19:06 +0000 |
| commit | 94e8847d674388c3c8ac663fa4912bb8029b2951 (patch) | |
| tree | 8e7ffbce4b7d253f05d0bb58ea6430aae8e1b065 /ice40 | |
| parent | 5fc3e8e4d2d82396e8ade480192379ccff95a931 (diff) | |
| download | nextpnr-94e8847d674388c3c8ac663fa4912bb8029b2951.tar.gz nextpnr-94e8847d674388c3c8ac663fa4912bb8029b2951.tar.bz2 nextpnr-94e8847d674388c3c8ac663fa4912bb8029b2951.zip | |
cleanup: Spelling fixes
Signed-off-by: D. Shah <dave@ds0.me>
Diffstat (limited to 'ice40')
| -rw-r--r-- | ice40/arch.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/ice40/arch.h b/ice40/arch.h index 1de39c33..fbf26e78 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -833,7 +833,7 @@ struct Arch : BaseCtx bool logicCellsCompatible(const CellInfo **it, const size_t size) const; // ------------------------------------------------- - // Assign architecure-specific arguments to nets and cells, which must be + // Assign architecture-specific arguments to nets and cells, which must be // called between packing or further // netlist modifications, and validity checks void assignArchInfo(); |