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| | * Arch API: New specification for timing port classesDavid Shah2018-08-082-22/+52
| | * clangformatEddie Hung2018-08-062-16/+20
| | * Merge branch 'master' into assign_budget_speedupEddie Hung2018-08-061-2/+17
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| | * | Add new Arch::isIOCell() API functionEddie Hung2018-08-062-0/+7
| * | | Moved option to commonMiodrag Milanovic2018-08-081-1/+0
| * | | clangformatMiodrag Milanovic2018-08-081-4/+4
| * | | Merge remote-tracking branch 'origin/master' into common_mainMiodrag Milanovic2018-08-085-100/+114
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| * | | Added project loaderMiodrag Milanovic2018-08-062-0/+72
| * | | Fix message for pcf loadingMiodrag Milanovic2018-08-051-1/+1
| * | | Added command parser and common implementationMiodrag Milanovic2018-08-051-355/+111
* | | | Get rid of old iCE40 id_ Arch membersClifford Wolf2018-08-086-59/+36
* | | | Get rid of PortPin and BelType (ice40, generic, docs)Clifford Wolf2018-08-0811-257/+125
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* | | ice40's getBudgetOverride() to return correct delay for different devicesEddie Hung2018-08-061-2/+17
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* | Fix ice40's getBudgetOverride() to override only for COUT -> CINEddie Hung2018-08-061-1/+1
* | Change getBudgetOverride() signature to return bool and modify budget in placeEddie Hung2018-08-062-5/+7
* | Restore initial assign_budget() call after pack(), restrict call after initia...Eddie Hung2018-08-051-0/+1
* | API change: Use CellInfo* and NetInfo* as cell/net handles (Python bindings)David Shah2018-08-051-9/+9
* | API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40)Clifford Wolf2018-08-054-85/+82
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* clangformatClifford Wolf2018-08-055-97/+84
* Fix bug in ice40 estimateDelay()Clifford Wolf2018-08-041-4/+6
* Use faster model for ice40 predictDelay()Clifford Wolf2018-08-041-1/+6
* Add new iCE40 delay estimator and delay predictorClifford Wolf2018-08-045-121/+343
* ice40: Bitstream gen for LUT permutationDavid Shah2018-08-041-8/+78
* Add generation of models to tmfuzzClifford Wolf2018-08-043-9/+184
* Refactor ice40 timing fuzzer used to create delay estimatesClifford Wolf2018-08-045-61/+180
* Fix bug in ice40 chipdby.py add_wire() that moves some wires to X0/Y0Clifford Wolf2018-08-041-3/+7
* Remove SVG functionality from ice40 mainClifford Wolf2018-08-041-31/+0
* Merge branch 'master' of github.com:YosysHQ/nextpnr into lutpermClifford Wolf2018-08-048-571/+324
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| * Merge branch 'master' into slack_redist_freqEddie Hung2018-08-039-565/+316
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| | * Merge pull request #23 from daveshah1/use_placeconstrDavid Shah2018-08-048-564/+311
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| | | * clangformatDavid Shah2018-08-043-3/+4
| | | * Tidy upDavid Shah2018-08-042-2/+2
| | | * Add constraint weight as a command line optionDavid Shah2018-08-033-1/+14
| | | * Fixing constraint placement bugsDavid Shah2018-08-033-4/+10
| | | * Fixing relative constraint implementationDavid Shah2018-08-031-1/+2
| | | * Reworking packer and placer to use new generic rel legaliserDavid Shah2018-08-032-1/+4
| | | * Remove old place legaliser, set placement constraints instead (currently igno...David Shah2018-08-034-562/+285
| | * | ice40: Add SB_GB timing to databaseDavid Shah2018-08-041-1/+5
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| * / Auto frequency only if --freq 0 is setEddie Hung2018-08-031-7/+10
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* | Proper ice40 wire typesClifford Wolf2018-08-035-57/+155
* | Add iCE40 pseudo-pips for lut permutationClifford Wolf2018-08-036-27/+157
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* Merge pull request #21 from daveshah1/promote_logic_globalsClifford Wolf2018-08-031-10/+40
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| * ice40: Promote 'logic' globals as well as clock/enable/resetDavid Shah2018-08-031-10/+40
* | Merge pull request #22 from YosysHQ/routethruClifford Wolf2018-08-034-15/+129
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| * | ice40: Add bitstream gen for routethru LUTsDavid Shah2018-08-031-9/+58
| * | Add LUT route-through pips to iCE40 architecture databaseClifford Wolf2018-08-023-6/+71
* | | Make worker genericMiodrag Milanovic2018-08-021-2/+4
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* | Merge pull request #11 from mmicko/project_loadMiodrag Milanović2018-08-021-0/+9
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| * | preserve command line parameters for project loadMiodrag Milanovic2018-08-021-0/+9
* | | ice40: Use real cell timingsDavid Shah2018-08-023-28/+24
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