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* Add Python helper functions for floorplanningDavid Shah2019-03-221-0/+7
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Fix u4k in external chipdb mode.Marcin Kościelnicki2019-03-191-3/+3
| | | | Signed-off-by: Marcin Kościelnicki <marcin@symbioticeda.com>
* ice40: u4k merge fixDavid Shah2019-02-251-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #239 from YosysHQ/dsp_casc_dummy_wiresDavid Shah2019-02-252-0/+24
|\ | | | | ice40: Add DSP SIGNEXTIN/OUT and ACCUMCI/O ports
| * ice40: Add DSP SIGNEXTIN/OUT and ACCUMCI/O portsDavid Shah2019-02-212-0/+24
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | ice40: support u4kSimon Schubert2019-02-2313-13/+57
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* ice40: Fix timing class of 'padin' GB outputsDavid Shah2019-02-201-1/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Merge branch 'master' into mmaped_chipdbMiodrag Milanović2019-02-121-1/+8
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| * ice40: PLLs can't conflict with themselvesDavid Shah2019-02-091-0/+2
| | | | | | | | | | | | Fixes error building testcase from #145 Signed-off-by: David Shah <dave@ds0.me>
| * ice40: Don't create PLLOUT_B buffer for single-output PLL variantsDavid Shah2019-02-091-1/+6
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Fix according to comments on PRMiodrag Milanovic2019-02-101-1/+1
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* | Load chipdb from filesystem as optionMiodrag Milanovic2019-02-093-83/+114
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* Merge pull request #220 from YosysHQ/coi3Eddie Hung2019-01-291-6/+9
|\ | | | | ice40: Add budget override for CO->I3 path
| * [ice40] Refactor Arch::getBudgetOverride()Eddie Hung2019-01-291-29/+9
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| * ice40: Add budget override for CO->I3 pathDavid Shah2019-01-271-0/+23
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | timing: Path related fixesDavid Shah2019-01-272-6/+33
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #211 from smunaut/ice40_ram_attrsDavid Shah2019-01-211-0/+4
|\ | | | | ice40/pack: Copy attributes to packed cell
| * ice40/pack: Copy attributes to packed RAM cellsSylvain Munaut2019-01-191-0/+4
| | | | | | | | | | | | | | Useful to allow manual placement of SPRAM/EBR using BEL attribute for instance Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | ice40: Add error message if a selected site is not Global Buffer capableSylvain Munaut2019-01-181-0/+4
|/ | | | | | ... rather than assert()-out during the call to getWireBelPins() call Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add timing data for all IO modesDavid Shah2019-01-072-3/+67
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Improve handling of unconstrained IODavid Shah2018-12-263-3/+23
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Add PCF support for -pullup, -pullup_resistor and -nowarnDavid Shah2018-12-202-4/+45
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ice40: Fix LOCK feedthrough insertion with carry or >8 LUTsDavid Shah2018-12-201-4/+10
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ci: Add attosoc smoketest for ice40David Shah2018-12-088-0/+3185
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Merge pull request #163 from daveshah1/timing_optDavid Shah2018-12-073-2/+17
|\ | | | | Adding criticality calculation and experimental timing optimisation pass
| * timing_opt: Reduce iterations to 30, tidy up loggingDavid Shah2018-12-061-2/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * timing_opt: Improve heuristicsDavid Shah2018-12-061-1/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * timing_opt: Make an optional pass controlled by command lineDavid Shah2018-12-062-3/+11
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * clangformatDavid Shah2018-12-061-3/+4
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * timing_opt: Debugging and integrationDavid Shah2018-12-061-1/+8
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ice40: Report error for unsupported PLL FEEDBACK_PATH valuesDavid Shah2018-12-061-7/+11
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ice40: Improve bitstream error handlingDavid Shah2018-12-061-2/+10
|/ | | | | | Fixes #161 and provides a clearer error for #170 Signed-off-by: David Shah <dave@ds0.me>
* clangformatDavid Shah2018-12-062-2/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Put debug logging behind ctx->debugDavid Shah2018-12-061-3/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Fix carry chain splittingDavid Shah2018-12-051-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Don't split carry chain in simple feed-out casesDavid Shah2018-12-041-7/+50
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Include I3 connectivity in chainDavid Shah2018-12-041-23/+25
| | | | | | Thanks @smunaut Signed-off-by: David Shah <dave@ds0.me>
* ice40: add reset global promotion threshold.whitequark2018-12-041-1/+3
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* ice40: Add support for placing SB_LEDDA_IP block.Daniel Serpell2018-12-015-1/+26
| | | | Signed-off-by: Daniel Serpell <daniel.serpell@gmail.com>
* ice40: Add a warning for unconstrained IODavid Shah2018-11-291-6/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Improve reporting of unknown cell typesDavid Shah2018-11-291-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #157 from whitequark/fanout-threshDavid Shah2018-11-291-1/+1
|\ | | | | ice40: raise CE global promotion threshold
| * ice40: raise CE global promotion threshold.whitequark2018-11-291-1/+1
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* | ice40: print fanout of nets promoted to globals.whitequark2018-11-281-7/+11
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* Merge pull request #155 from smunaut/issue_151David Shah2018-11-281-48/+48
|\ | | | | ice40: Update the way LVDS inputs are handled during bitstream generation
| * ice40: Update the way LVDS inputs are handled during bitstream generationSylvain Munaut2018-11-281-48/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Instead of "patching" input_en, we completely separate config for normal and LVDS pair. - For normal pair, nothing changes - For LVDS pairs, the IE/REN bits are always set as if the input buffer are disabled. Then if input_en was set to 1 (i.e. the input is actually for something), then we set the IoCtrl.LVDS bit. - Also for LVDS, if input is used, pullups are forcibly disabled. * When scanning for unused IOs, never process those part of a LVDS pair. They will have been configured by the complement Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | ice40: Try to be helpful and suggest using PAD PLL instead of CORESylvain Munaut2018-11-281-2/+14
| | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | ice40: Revamp the whole PLL placement/validity check logicSylvain Munaut2018-11-281-72/+200
|/ | | | | | | | | | | | | | | | | We do a pre-pass on all the PLLs to place them before packing. To place them: - First pass with all the PADs PLLs since those can only fit at one specific BEL depending on the input connection - Second pass with all the dual outputs CORE PLLs. Those can go anywhere where there is no conflicts with their A & B outputs and used IO pins - Third pass with the single output CORE PLLs. Those have the least constrains. During theses passes, we also check the validity of all their connections. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Finer-grained control of global promotionDavid Shah2018-11-272-3/+14
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: During global promotion, only promote if this will actually fit !Sylvain Munaut2018-11-261-6/+32
| | | | | | | | We need to take into account the global networks that are already used and possibly locked to know what we can promote since all networks can't drive resets / clock-enables Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
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