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| * [ice40] Refactor Arch::getBudgetOverride()Eddie Hung2019-01-291-29/+9
| * ice40: Add budget override for CO->I3 pathDavid Shah2019-01-271-0/+23
* | timing: Path related fixesDavid Shah2019-01-271-5/+29
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* ice40: Add timing data for all IO modesDavid Shah2019-01-071-3/+65
* timing_opt: Reduce iterations to 30, tidy up loggingDavid Shah2018-12-061-2/+1
* timing_opt: Make an optional pass controlled by command lineDavid Shah2018-12-061-3/+8
* clangformatDavid Shah2018-12-061-3/+4
* timing_opt: Debugging and integrationDavid Shah2018-12-061-1/+8
* ice40: Add support for placing SB_LEDDA_IP block.Daniel Serpell2018-12-011-0/+4
* Improve reporting of unknown cell typesDavid Shah2018-11-291-1/+1
* ice40: Add support for SB_RGBA_DRVSylvain Munaut2018-11-191-0/+4
* ice40: Add support for SB_GB_IOSylvain Munaut2018-11-191-0/+1
* ice40: Introduce the concept of forPadIn SB_GBSylvain Munaut2018-11-191-0/+2
* ice40/arch: Add helper to check if a BEL is LOCKED or notSylvain Munaut2018-11-191-0/+19
* Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-131-4/+4
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| * [ice40] getBudgetOverride() to use constrained Z not placed ZEddie Hung2018-11-131-4/+4
* | timing: Fix handling of clock inputsDavid Shah2018-11-121-2/+2
* | Working on multi-clock analysisDavid Shah2018-11-121-6/+4
* | timing: iCE40 Arch API changes for clocking infoDavid Shah2018-11-121-18/+62
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* Merge pull request #88 from YosysHQ/issue72Eddie Hung2018-10-111-6/+13
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| * [ice40] TimingPortClass of LC.O ports without any inputs now TMG_IGNOREEddie Hung2018-09-151-6/+13
* | clangformatDavid Shah2018-09-301-1/+0
* | ice40: Validity check for LVDS IODavid Shah2018-09-241-0/+2
* | ice40: Remove obsolete belType memberDavid Shah2018-09-241-1/+0
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* Add more missing iCE40 gfx (LP/HX is complete now)Clifford Wolf2018-08-191-0/+46
* Add iCE40 gfx for IO span-4 cornersClifford Wolf2018-08-191-1/+1
* Add iCE40 gfx for span-4 wires between IO tilesClifford Wolf2018-08-191-3/+9
* Merge pull request #47 from YosysHQ/settings_propagateClifford Wolf2018-08-181-11/+2
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| * Use settings for placer1 and router1Miodrag Milanovic2018-08-091-11/+2
* | Improve iCE40 gfx for IO tiles and RAM tilesClifford Wolf2018-08-181-2/+6
* | Add ice40 wire attributes (grid position, segment list)Clifford Wolf2018-08-181-0/+33
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* Merge branch 'master' of github.com:YosysHQ/nextpnr into constidsClifford Wolf2018-08-081-22/+77
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| * ice40: Add error for unknown cell type when getting timing infoDavid Shah2018-08-081-1/+3
| * Arch API: Removing Arch::isIOCellDavid Shah2018-08-081-2/+0
| * ice40: Add timing arcs through global buffersDavid Shah2018-08-081-0/+4
| * timing: Debugging implementation of new timing APIDavid Shah2018-08-081-1/+1
| * ice40: Timing arch fixDavid Shah2018-08-081-3/+17
| * timing: Update to new use API (currently broken)David Shah2018-08-081-2/+2
| * Arch API: New specification for timing port classesDavid Shah2018-08-081-18/+50
| * clangformatEddie Hung2018-08-061-10/+12
| * Merge branch 'master' into assign_budget_speedupEddie Hung2018-08-061-2/+17
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| * | Add new Arch::isIOCell() API functionEddie Hung2018-08-061-0/+5
* | | Get rid of old iCE40 id_ Arch membersClifford Wolf2018-08-081-43/+20
* | | Get rid of PortPin and BelType (ice40, generic, docs)Clifford Wolf2018-08-081-110/+20
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* | ice40's getBudgetOverride() to return correct delay for different devicesEddie Hung2018-08-061-2/+17
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* Fix ice40's getBudgetOverride() to override only for COUT -> CINEddie Hung2018-08-061-1/+1
* Change getBudgetOverride() signature to return bool and modify budget in placeEddie Hung2018-08-061-4/+6
* API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40)Clifford Wolf2018-08-051-3/+3
* clangformatClifford Wolf2018-08-051-34/+32
* Add new iCE40 delay estimator and delay predictorClifford Wolf2018-08-041-58/+0
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