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* fabulous: Support for configurable LUT sizegatecat2023-04-132-2/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* viaduct: Add support for GUIsgatecat2023-04-117-42/+117
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: Fix bel names for pass bels in v2 formatgatecat2023-04-052-2/+14
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cmake: Make HeAP placer always-enabledgatecat2023-03-171-10/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: Misc improvementsgatecat2023-02-283-2/+24
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: Support for complex flops in PnRgatecat2023-02-284-4/+37
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: Add timing model for carriesgatecat2023-02-271-0/+20
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: LUT permutation supportgatecat2023-02-274-2/+102
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: Global constant wires schemegatecat2023-02-236-15/+140
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: Add support for packing carry chainsgatecat2023-02-213-10/+122
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: Further tweak magic numbersgatecat2023-02-161-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: Add fake timingsgatecat2023-02-162-6/+46
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: Improve names for BRAM belsgatecat2023-02-102-6/+25
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* api: add explain_invalid option to isBelLocationValidgatecat2022-12-076-7/+10
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: ArcBounds -> BoundingBoxgatecat2022-12-074-6/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* viaduct: Fix constant connectivitygatecat2022-12-061-0/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* api: Make NetInfo* of checkPipAvailForNet constgatecat2022-12-023-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: Tweak delay estimategatecat2022-11-101-0/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: Pack, validity check and FASM support for muxesgatecat2022-09-304-5/+84
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: Add split MUX belsgatecat2022-09-302-1/+50
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: fix, but disable, IO configurationgatecat2022-09-161-0/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* fabulous: Add a viaduct uarchgatecat2022-09-0912-1/+1637
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* viaduct: Allow passing command line options to uarch with -ogatecat2022-08-151-0/+14
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-103-49/+46
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* generic: addBelPin with direction as an arggatecat2022-08-043-25/+12
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* netlist: Add PseudoCell APIgatecat2022-07-081-1/+1
| | | | | | | | | | | | | | | When implementing concepts such as partition pins or deliberately split nets, there's a need for something that looks like a cell (starts/ends routing with pins on nets, has timing data) but isn't mapped to a fixed bel in the architecture, but instead can have pin mappings defined at runtime. The PseudoCell allows this by providing an alternate, virtual-function based API for such cells. When a cell has `pseudo_cell` used, instead of calling functions such as getBelPinWire, getBelLocation or getCellDelay in the Arch API; such data is provided by the cell itself, fully flexible at runtime regardless of arch, via methods on the PseudoCell implementation.
* generic: Use arch_pybindings_sharedgatecat2022-07-041-105/+12
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* generic: Add some extra helpers for viaduct uarchesgatecat2022-05-024-4/+52
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* generic: Add missing uarch guardgatecat2022-04-271-1/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* generic: Allow bel pins without wiresgatecat2022-04-041-3/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Switch to potentially-sparse net users arraygatecat2022-02-274-7/+8
| | | | | | | | This uses a new data structure for net.users that allows gaps, so removing a port from a net is no longer an O(n) operation on the number of users the net has. Signed-off-by: gatecat <gatecat@ds0.me>
* okami: new Viaduct archLofty2022-02-247-1/+638
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* refactor: New member functions to replace design_utilsgatecat2022-02-185-20/+20
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: Use cell member functions to add portsgatecat2022-02-161-15/+8
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: New NetInfo and CellInfo constructorsgatecat2022-02-162-11/+5
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* viaduct: Allow constraining only cascades without fanoutgatecat2022-02-042-2/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* generic: Add missing Pip vector bindinggatecat2022-02-042-0/+13
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Viaduct API for a hybrid between generic and full-custom archgatecat2022-01-0418-28/+1055
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* generic: Refactor for faster performancegatecat2021-12-306-205/+319
| | | | | | | | This won't affect Python-built arches significantly; but will be useful for the future 'viaduct' functionality where generic routing graphs can be built on the C++ side; too. Signed-off-by: gatecat <gatecat@ds0.me>
* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-192-5/+6
| | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
* Fixing old emails and names in copyrightsgatecat2021-06-129-11/+11
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib in most remaining codegatecat2021-06-021-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Using hashlib in archesgatecat2021-06-025-36/+21
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Use hashlib for core netlist structuresgatecat2021-06-023-16/+19
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add stub cluster API impl for remaining archesgatecat2021-05-062-0/+12
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add "checkPipAvailForNet" to Arch API.Keith Rothman2021-03-222-0/+7
| | | | | | | | This is important for distiguishing valid pseudo pips in the FPGA interchange arch. This also avoids a double or triple lookup of pip->net map. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-152-6/+20
| | | | | | | | | | | | | | | | | | | "nextpnr.h" is no longer the god header. Important improvements: - Functions in log.h can be used without including BaseCtx/Arch/Context. This means that log_X functions can be called without included "nextpnr.h" - NPNR_ASSERT can be used without including "nextpnr.h" by including "nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in any header file. - Types defined in "archdefs.h" are now available without including BaseCtx/Arch/Context. This means that utility classes that will be used inside of BaseCtx/Arch/Context can be defined safely in a self-contained header. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Change CellInfo in getBelPinsForCellPin to be const.Keith Rothman2021-02-232-2/+2
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-194-60/+31
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* generic: Don't generate Vcc if not neededgatecat2021-02-171-5/+7
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-07 11:53:30 +0000