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* Use hashlib for core netlist structuresgatecat2021-06-025-12/+14
* Add hash() member functionsgatecat2021-06-021-0/+5
* interchange: Add LIFCL-40 EVN testsgatecat2021-06-0110-1/+82
* interchange: Add macro parameter mappinggatecat2021-05-212-3/+53
* interchange: Don't error out on missing cell portsgatecat2021-05-212-2/+3
* interchange: Add LUTRAM testgatecat2021-05-216-0/+169
* interchange: Preliminary implementation of macro expansiongatecat2021-05-213-0/+116
* interchange: Add macro param map rules to chipdbgatecat2021-05-211-0/+24
* interchange: Add macro data to chipdbgatecat2021-05-211-1/+51
* interchange: phys: add site instance idstr for pseudo tile PIPsAlessandro Comodi2021-05-191-0/+19
* Run clangformatgatecat2021-05-162-5/+7
* interchange: pseudo pips: fix illegal tile pseudo PIPsAlessandro Comodi2021-05-143-21/+62
* interchange: site router: add valid pips list to check during routingAlessandro Comodi2021-05-133-11/+59
* interchange: arch: do not allow site pips within sitesAlessandro Comodi2021-05-121-6/+0
* interchange: Fix bounding box computationgatecat2021-05-111-2/+2
* interchange: site router: fix log messagesAlessandro Comodi2021-05-101-3/+3
* interchange: site router: fix illegal site thru pathsAlessandro Comodi2021-05-102-0/+23
* interchange: Adding a basic global buffer placergatecat2021-05-073-32/+132
* interchange: Initial global routing implementationgatecat2021-05-073-0/+222
* interchange: Add more global cell infogatecat2021-05-071-1/+14
* Add stub cluster API impl for remaining archesgatecat2021-05-062-0/+15
* interchange/nexus: Add counter examplegatecat2021-04-308-3/+61
* interchange: Implement getWireTypegatecat2021-04-301-1/+18
* interchange: Add wire types to chipdbgatecat2021-04-301-1/+17
* Merge pull request #683 from antmicro/interchange-allow-loc-keywordgatecat2021-04-201-2/+4
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| * interchange: allow LOC keyword in XDC filesJan Kowalewski2021-04-201-2/+4
* | interchange: Handle disconnected/missing cell pinsgatecat2021-04-193-6/+56
* | interchange: Add default cell connections to chipdbgatecat2021-04-191-1/+24
* | Add Python bindings for placement testsgatecat2021-04-151-0/+5
* | Merge pull request #678 from acomodi/initial-fasm-generationgatecat2021-04-1420-70/+135
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| * | interchange: add FASM generation target and clean-up testsAlessandro Comodi2021-04-1420-70/+135
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* / Hash table refactoringgatecat2021-04-146-10/+11
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* interchange: Allow pseudo-cells with no input pinsgatecat2021-04-131-14/+35
* clangformatgatecat2021-04-128-133/+134
* interchange: Disambiguate cell and bel pins when creating Vcc tiesgatecat2021-04-091-6/+10
* [interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined.Keith Rothman2021-04-061-1/+16
* [interchange] Remove requirement to have wire_lut.Keith Rothman2021-04-063-6/+7
* [interchange] Fix invalid use of local variables due to refactoring.Keith Rothman2021-04-063-6/+7
* [interchange] Prevent site router from generating incorrect LUTs.Keith Rothman2021-04-063-42/+102
* [interchange] Scale edge cost of pseudo pips.Keith Rothman2021-04-062-5/+12
* [interchange] Fix missing inline methods in site_arch.impl.hKeith Rothman2021-04-062-8/+9
* [interchange] Disallow site edges during general routing.Keith Rothman2021-04-062-5/+23
* [interchange] Add crude pseudo pip model.Keith Rothman2021-04-066-7/+717
* Merge pull request #661 from litghost/document_site_routergatecat2021-04-061-10/+58
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| * [interchange] Add some documentation for the site router.Keith Rothman2021-04-051-10/+58
* | Merge pull request #657 from acomodi/interchange-counter-multi-boardgatecat2021-04-065-23/+25
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| * interchange: counter: testing on multiple boardsAlessandro Comodi2021-04-015-23/+25
* | [interchange] Update to v6 of FPGA interchange chipdb.Keith Rothman2021-04-013-2/+12
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* Merge pull request #646 from YosysHQ/gatecat/nexus-cmakegatecat2021-03-3113-126/+368
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| * interchange: Fix nexus cmake review commentsgatecat2021-03-313-9/+4
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