Merge pull request #646 from YosysHQ/gatecat/nexus-cmake

fpga_interchange: Add CMake support for Nexus/prjoxide

13 files changed, 368 insertions, 126 deletions

diff --git a/fpga_interchange/examples/chipdb.cmake b/fpga_interchange/examples/chipdb.cmake
index 4705c0bc..a060576d 100644
--- a/fpga_interchange/examples/chipdb.cmake
+++ b/fpga_interchange/examples/chipdb.cmake
@@ -1,71 +1,5 @@
-function(create_rapidwright_device_db)
-    # ~~~
-    # create_rapidwright_device_db(
-    #    device <common device>
-    #    part <part>
-    #    output_target <output device target>
-    # )
-    # ~~~
-    #
-    # Generates a device database from RapidWright
-    #
-    # If output_target is specified, the output_target_name variable
-    # is set to the generated output_device_file target.
-    #
-    # Arguments:
-    #   - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
-    #             share the same xc7a35t device prefix
-    #   - part: one among the parts available for a given device
-    #   - output_target: variable name that will hold the output device target for the parent scope
-    #
-    # Targets generated:
-    #   - rapidwright-<device>-device
-
-    set(options)
-    set(oneValueArgs device part output_target)
-    set(multiValueArgs)
-
-    cmake_parse_arguments(
-        create_rapidwright_device_db
-        "${options}"
-        "${oneValueArgs}"
-        "${multiValueArgs}"
-        ${ARGN}
-    )
-
-    set(device ${create_rapidwright_device_db_device})
-    set(part ${create_rapidwright_device_db_part})
-    set(output_target ${create_rapidwright_device_db_output_target})
-    set(rapidwright_device_db ${CMAKE_CURRENT_BINARY_DIR}/${part}.device)
-    add_custom_command(
-        OUTPUT ${rapidwright_device_db}
-        COMMAND
-            RAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH}
-            ${INVOKE_RAPIDWRIGHT} ${JAVA_HEAP_SPACE}
-            com.xilinx.rapidwright.interchange.DeviceResourcesExample
-            ${part}
-        DEPENDS
-            ${INVOKE_RAPIDWRIGHT}
-    )
-
-    add_custom_target(rapidwright-${device}-device DEPENDS ${rapidwright_device_db})
-    set_property(TARGET rapidwright-${device}-device PROPERTY LOCATION ${rapidwright_device_db})
-
-    add_custom_target(rapidwright-${device}-device-yaml
-        COMMAND
-            ${PYTHON_EXECUTABLE} -mfpga_interchange.convert
-                --schema_dir ${INTERCHANGE_SCHEMA_PATH}
-                --schema device
-                --input_format capnp
-                --output_format yaml
-                ${rapidwright_device_db}
-                ${rapidwright_device_db}.yaml
-        DEPENDS ${rapidwright_device_db})
-
-    if (DEFINED output_target)
-        set(${output_target} rapidwright-${device}-device PARENT_SCOPE)
-    endif()
-endfunction()
+include(${family}/examples/chipdb_xilinx.cmake)
+include(${family}/examples/chipdb_nexus.cmake)
 
 function(create_patched_device_db)
     # ~~~
@@ -156,72 +90,77 @@ function(create_patched_device_db)
     endif()
 endfunction()
 
-function(generate_xc7_device_db)
+function(patch_device_with_prim_lib)
     # ~~~
-    # generate_xc7_device_db(
+    # patch_device_with_prim_lib(
     #    device <common device>
-    #    part <part>
-    #    device_target <variable name for device target>
+    #    yosys_script <yosys script>
+    #    input_device <input device target>
+    #    output_target <output device target>
     # )
     # ~~~
     #
-    # Generates a chipdb BBA file, starting from a RapidWright device database which is then patched.
-    # Patches applied:
-    #   - constraints patch
-    #   - luts patch
+    # Patches an input device with a primitive library from Yosys
+    #
+    # If output_target is specified, the variable named as the output_target
+    # parameter value is set to the generated output_device_file target.
     #
     # Arguments:
     #   - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
-    #             share the same xc7a35t device prefix
-    #   - part: one among the parts available for a given device
-    #   - device_target: variable name that will hold the output device target for the parent scope
+    #             share the same xc7a35t device prefix.
+    #   - yosys_script: yosys script to produce cell library
+    #   - input_device: target for the device that needs to be patched
+    #   - output_target: variable name that will hold the output device target for the parent scope
+    #
+    # Targets generated:
+    #   - prims-<device>-device
 
     set(options)
-    set(oneValueArgs device part device_target)
+    set(oneValueArgs device yosys_script input_device output_target)
     set(multiValueArgs)
 
     cmake_parse_arguments(
-        create_rapidwright_device_db
+        patch_device_with_prim_lib
         "${options}"
         "${oneValueArgs}"
         "${multiValueArgs}"
         ${ARGN}
     )
 
-    set(device ${create_rapidwright_device_db_device})
-    set(part ${create_rapidwright_device_db_part})
-    set(device_target ${create_rapidwright_device_db_device_target})
+    set(device ${patch_device_with_prim_lib_device})
+    set(yosys_script ${patch_device_with_prim_lib_yosys_script})
+    set(input_device ${patch_device_with_prim_lib_input_device})
+    set(output_target ${patch_device_with_prim_lib_output_target})
 
-    create_rapidwright_device_db(
-        device ${device}
-        part ${part}
-        output_target rapidwright_device
-    )
+    get_target_property(input_device_loc ${input_device} LOCATION)
+    set(output_device_file ${CMAKE_CURRENT_BINARY_DIR}/${device}_prim_lib.device)
+    set(output_json_file ${CMAKE_CURRENT_BINARY_DIR}/${device}_prim_lib.json)
 
-    # Generate constraints patch
-    create_patched_device_db(
-        device ${device}
-        patch_name constraints
-        patch_path constraints
-        patch_format yaml
-        patch_data ${PYTHON_INTERCHANGE_PATH}/test_data/series7_constraints.yaml
-        input_device ${rapidwright_device}
-        output_target constraints_device
+    add_custom_command(
+        OUTPUT ${output_json_file}
+        COMMAND
+            yosys -p '${yosys_script}\; write_json ${output_json_file}'
     )
 
-    # Generate lut constraints patch
-    create_patched_device_db(
-        device ${device}
-        patch_name constraints-luts
-        patch_path lutDefinitions
-        patch_format yaml
-        patch_data ${PYTHON_INTERCHANGE_PATH}/test_data/series7_luts.yaml
-        input_device ${constraints_device}
-        output_target constraints_luts_device
+    add_custom_command(
+        OUTPUT ${output_device_file}
+        COMMAND
+            ${PYTHON_EXECUTABLE} -mfpga_interchange.add_prim_lib
+                --schema_dir ${INTERCHANGE_SCHEMA_PATH}
+                ${input_device_loc}
+                ${output_json_file}
+                ${output_device_file}
+        DEPENDS
+            ${input_device}
+            ${input_device_loc}
+            ${output_json_file}
     )
 
-    if(DEFINED device_target)
-        set(${device_target} ${constraints_luts_device} PARENT_SCOPE)
+    add_custom_target(prims-${device}-device DEPENDS ${output_device_file})
+    set_property(TARGET prims-${device}-device PROPERTY LOCATION ${output_device_file})
+
+    if (DEFINED output_target)
+        set(${output_target} prims-${device}-device PARENT_SCOPE)
     endif()
 endfunction()
 
diff --git a/fpga_interchange/examples/chipdb_nexus.cmake b/fpga_interchange/examples/chipdb_nexus.cmake
new file mode 100644
index 00000000..4ea180c5
--- /dev/null
+++ b/fpga_interchange/examples/chipdb_nexus.cmake
@@ -0,0 +1,101 @@
+function(create_prjoxide_device_db)
+    # ~~~
+    # create_prjoxide_device_db(
+    #    device <common device>
+    #    output_target <output device target>
+    # )
+    # ~~~
+    #
+    # Generates a device database from Project Oxide
+    #
+    # If output_target is specified, the output_target_name variable
+    # is set to the generated output_device_file target.
+    #
+    # Arguments:
+    #   - device: common device name of a set of parts. E.g. LIFCL-17
+    #   - output_target: variable name that will hold the output device target for the parent scope
+    #
+    # Targets generated:
+    #   - prjoxide-<device>-device
+    set(options)
+    set(oneValueArgs device output_target)
+    set(multiValueArgs)
+
+    cmake_parse_arguments(
+        create_prjoxide_device_db
+        "${options}"
+        "${oneValueArgs}"
+        "${multiValueArgs}"
+        ${ARGN}
+    )
+
+    set(device ${create_prjoxide_device_db_device})
+    set(output_target ${create_prjoxide_device_db_output_target})
+    set(prjoxide_device_db ${CMAKE_CURRENT_BINARY_DIR}/${device}.device)
+    add_custom_command(
+        OUTPUT ${prjoxide_device_db}
+        COMMAND
+            ${PRJOXIDE_PREFIX}/bin/prjoxide
+            interchange-export
+            ${device}
+            ${prjoxide_device_db}
+        DEPENDS
+            ${PRJOXIDE_PREFIX}/bin/prjoxide
+    )
+
+    add_custom_target(prjoxide-${device}-device DEPENDS ${prjoxide_device_db})
+    set_property(TARGET prjoxide-${device}-device PROPERTY LOCATION ${prjoxide_device_db})
+
+    if (DEFINED output_target)
+        set(${output_target} prjoxide-${device}-device PARENT_SCOPE)
+    endif()
+
+endfunction()
+
+function(generate_nexus_device_db)
+    # ~~~
+    # generate_nexus_device_db(
+    #    device <common device>
+    #    device_target <variable name for device target>
+    # )
+    # ~~~
+    #
+    # Generates a chipdb BBA file, starting from a Project Oxide device database.
+    # Patches applied:
+    #   - primitive library from Yosys
+    #
+    # Arguments:
+    #   - device: common device name of a set of parts. E.g. LIFCL-17
+    #   - device_target: variable name that will hold the output device target for the parent scope
+    set(options)
+    set(oneValueArgs device device_target)
+    set(multiValueArgs)
+
+    cmake_parse_arguments(
+        generate_nexus_device_db
+        "${options}"
+        "${oneValueArgs}"
+        "${multiValueArgs}"
+        ${ARGN}
+    )
+
+    set(device ${generate_nexus_device_db_device})
+    set(device_target ${generate_nexus_device_db_device_target})
+
+    create_prjoxide_device_db(
+        device ${device}
+        output_target prjoxide_device
+    )
+
+    # Add primitive library
+    patch_device_with_prim_lib(
+        device ${device}
+        yosys_script synth_nexus
+        input_device ${prjoxide_device}
+        output_target prjoxide_prims_device
+    )
+
+    if(DEFINED device_target)
+        set(${device_target} ${prjoxide_prims_device} PARENT_SCOPE)
+    endif()
+endfunction()
diff --git a/fpga_interchange/examples/chipdb_xilinx.cmake b/fpga_interchange/examples/chipdb_xilinx.cmake
new file mode 100644
index 00000000..23b4d7f1
--- /dev/null
+++ b/fpga_interchange/examples/chipdb_xilinx.cmake
@@ -0,0 +1,138 @@
+function(create_rapidwright_device_db)
+    # ~~~
+    # create_rapidwright_device_db(
+    #    device <common device>
+    #    part <part>
+    #    output_target <output device target>
+    # )
+    # ~~~
+    #
+    # Generates a device database from RapidWright
+    #
+    # If output_target is specified, the output_target_name variable
+    # is set to the generated output_device_file target.
+    #
+    # Arguments:
+    #   - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
+    #             share the same xc7a35t device prefix
+    #   - part: one among the parts available for a given device
+    #   - output_target: variable name that will hold the output device target for the parent scope
+    #
+    # Targets generated:
+    #   - rapidwright-<device>-device
+
+    set(options)
+    set(oneValueArgs device part output_target)
+    set(multiValueArgs)
+
+    cmake_parse_arguments(
+        create_rapidwright_device_db
+        "${options}"
+        "${oneValueArgs}"
+        "${multiValueArgs}"
+        ${ARGN}
+    )
+
+    set(device ${create_rapidwright_device_db_device})
+    set(part ${create_rapidwright_device_db_part})
+    set(output_target ${create_rapidwright_device_db_output_target})
+    set(rapidwright_device_db ${CMAKE_CURRENT_BINARY_DIR}/${part}.device)
+    add_custom_command(
+        OUTPUT ${rapidwright_device_db}
+        COMMAND
+            RAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH}
+            ${INVOKE_RAPIDWRIGHT} ${JAVA_HEAP_SPACE}
+            com.xilinx.rapidwright.interchange.DeviceResourcesExample
+            ${part}
+        DEPENDS
+            ${INVOKE_RAPIDWRIGHT}
+    )
+
+    add_custom_target(rapidwright-${device}-device DEPENDS ${rapidwright_device_db})
+    set_property(TARGET rapidwright-${device}-device PROPERTY LOCATION ${rapidwright_device_db})
+
+    add_custom_target(rapidwright-${device}-device-yaml
+        COMMAND
+            ${PYTHON_EXECUTABLE} -mfpga_interchange.convert
+                --schema_dir ${INTERCHANGE_SCHEMA_PATH}
+                --schema device
+                --input_format capnp
+                --output_format yaml
+                ${rapidwright_device_db}
+                ${rapidwright_device_db}.yaml
+        DEPENDS ${rapidwright_device_db})
+
+    if (DEFINED output_target)
+        set(${output_target} rapidwright-${device}-device PARENT_SCOPE)
+    endif()
+endfunction()
+
+
+function(generate_xc7_device_db)
+    # ~~~
+    # generate_xc7_device_db(
+    #    device <common device>
+    #    part <part>
+    #    device_target <variable name for device target>
+    # )
+    # ~~~
+    #
+    # Generates a chipdb BBA file, starting from a RapidWright device database which is then patched.
+    # Patches applied:
+    #   - constraints patch
+    #   - luts patch
+    #
+    # Arguments:
+    #   - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
+    #             share the same xc7a35t device prefix
+    #   - part: one among the parts available for a given device
+    #   - device_target: variable name that will hold the output device target for the parent scope
+
+    set(options)
+    set(oneValueArgs device part device_target)
+    set(multiValueArgs)
+
+    cmake_parse_arguments(
+        create_rapidwright_device_db
+        "${options}"
+        "${oneValueArgs}"
+        "${multiValueArgs}"
+        ${ARGN}
+    )
+
+    set(device ${create_rapidwright_device_db_device})
+    set(part ${create_rapidwright_device_db_part})
+    set(device_target ${create_rapidwright_device_db_device_target})
+
+    create_rapidwright_device_db(
+        device ${device}
+        part ${part}
+        output_target rapidwright_device
+    )
+
+    # Generate constraints patch
+    create_patched_device_db(
+        device ${device}
+        patch_name constraints
+        patch_path constraints
+        patch_format yaml
+        patch_data ${PYTHON_INTERCHANGE_PATH}/test_data/series7_constraints.yaml
+        input_device ${rapidwright_device}
+        output_target constraints_device
+    )
+
+    # Generate lut constraints patch
+    create_patched_device_db(
+        device ${device}
+        patch_name constraints-luts
+        patch_path lutDefinitions
+        patch_format yaml
+        patch_data ${PYTHON_INTERCHANGE_PATH}/test_data/series7_luts.yaml
+        input_device ${constraints_device}
+        output_target constraints_luts_device
+    )
+
+    if(DEFINED device_target)
+        set(${device_target} ${constraints_luts_device} PARENT_SCOPE)
+    endif()
+endfunction()
diff --git a/fpga_interchange/examples/devices/CMakeLists.txt b/fpga_interchange/examples/devices/CMakeLists.txt
index 965e4aa8..ff01bd3c 100644
--- a/fpga_interchange/examples/devices/CMakeLists.txt
+++ b/fpga_interchange/examples/devices/CMakeLists.txt
@@ -5,3 +5,6 @@ add_subdirectory(xc7a200t)
 
 # Zynq-7 devices
 add_subdirectory(xc7z010)
+
+# Nexus devices
+add_subdirectory(LIFCL-17)
diff --git a/fpga_interchange/examples/devices/LIFCL-17/CMakeLists.txt b/fpga_interchange/examples/devices/LIFCL-17/CMakeLists.txt
new file mode 100644
index 00000000..572ff200
--- /dev/null
+++ b/fpga_interchange/examples/devices/LIFCL-17/CMakeLists.txt
@@ -0,0 +1,13 @@
+generate_nexus_device_db(
+    device LIFCL-17
+    device_target lifcl17_target
+)
+
+generate_chipdb(
+    family ${family}
+    device LIFCL-17
+    part LIFCL-17-7SG72C
+    device_target ${lifcl17_target}
+    device_config ${PYTHON_INTERCHANGE_PATH}/test_data/nexus_device_config.yaml
+    test_package QFN72
+)
diff --git a/fpga_interchange/examples/devices/LIFCL-17/test_data.yaml b/fpga_interchange/examples/devices/LIFCL-17/test_data.yaml
new file mode 100644
index 00000000..c4787eba
--- /dev/null
+++ b/fpga_interchange/examples/devices/LIFCL-17/test_data.yaml
@@ -0,0 +1,8 @@
+pip_test:
+    - src_wire: R3C3_PLC.PLC/JDI0_SLICEA
+      dst_wire: R3C3/JF0
+bel_pin_test:
+    - bel: R7C3_PLC.PLC/SLICEA_LUT0
+      pin: D
+      wire: R7C3_PLC.PLC/JD0_SLICEA
+
diff --git a/fpga_interchange/examples/tests.cmake b/fpga_interchange/examples/tests.cmake
index 115b4a36..930682a5 100644
--- a/fpga_interchange/examples/tests.cmake
+++ b/fpga_interchange/examples/tests.cmake
@@ -34,7 +34,7 @@ function(add_interchange_test)
     #   - test-fpga_interchange-<name>-phys     : interchange physical netlist
     #   - test-fpga_interchange-<name>-dcp     : design checkpoint with RapidWright
 
-    set(options)
+    set(options skip_dcp)
     set(oneValueArgs name family device package tcl xdc top techmap)
     set(multiValueArgs sources)
 
@@ -50,6 +50,7 @@ function(add_interchange_test)
     set(family ${add_interchange_test_family})
     set(device ${add_interchange_test_device})
     set(package ${add_interchange_test_package})
+    set(skip_dcp ${add_interchange_test_skip_dcp})
     set(top ${add_interchange_test_top})
     set(tcl ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_tcl})
     set(xdc ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_xdc})
@@ -246,23 +247,28 @@ function(add_interchange_test)
 
     add_custom_target(test-${family}-${name}-phys-yaml DEPENDS ${phys_yaml})
 
-    set(dcp ${CMAKE_CURRENT_BINARY_DIR}/${name}.dcp)
-    add_custom_command(
-        OUTPUT ${dcp}
-        COMMAND
-            RAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH}
-            ${INVOKE_RAPIDWRIGHT} ${JAVA_HEAP_SPACE}
-            com.xilinx.rapidwright.interchange.PhysicalNetlistToDcp
-            ${netlist} ${phys} ${xdc} ${dcp}
-        DEPENDS
-            ${INVOKE_RAPIDWRIGHT}
-            ${phys}
-            ${netlist}
-    )
+    if(skip_dcp)
+        add_dependencies(all-${family}-tests test-${family}-${name}-phys-yaml)
+        add_dependencies(all-${device}-tests test-${family}-${name}-phys-yaml)
+    else()
+        set(dcp ${CMAKE_CURRENT_BINARY_DIR}/${name}.dcp)
+        add_custom_command(
+            OUTPUT ${dcp}
+            COMMAND
+                RAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH}
+                ${INVOKE_RAPIDWRIGHT} ${JAVA_HEAP_SPACE}
+                com.xilinx.rapidwright.interchange.PhysicalNetlistToDcp
+                ${netlist} ${phys} ${xdc} ${dcp}
+            DEPENDS
+                ${INVOKE_RAPIDWRIGHT}
+                ${phys}
+                ${netlist}
+        )
 
-    add_custom_target(test-${family}-${name}-dcp DEPENDS ${dcp})
-    add_dependencies(all-${family}-tests test-${family}-${name}-dcp)
-    add_dependencies(all-${device}-tests test-${family}-${name}-dcp)
+        add_custom_target(test-${family}-${name}-dcp DEPENDS ${dcp})
+        add_dependencies(all-${family}-tests test-${family}-${name}-dcp)
+        add_dependencies(all-${device}-tests test-${family}-${name}-dcp)
+    endif()
 endfunction()
 
 function(add_interchange_group_test)
diff --git a/fpga_interchange/examples/tests/CMakeLists.txt b/fpga_interchange/examples/tests/CMakeLists.txt
index 40ec8a75..f58adc70 100644
--- a/fpga_interchange/examples/tests/CMakeLists.txt
+++ b/fpga_interchange/examples/tests/CMakeLists.txt
@@ -4,3 +4,4 @@ add_subdirectory(counter)
 add_subdirectory(ram)
 add_subdirectory(ff)
 add_subdirectory(lut)
+add_subdirectory(lut_nexus)
diff --git a/fpga_interchange/examples/tests/lut_nexus/CMakeLists.txt b/fpga_interchange/examples/tests/lut_nexus/CMakeLists.txt
new file mode 100644
index 00000000..1c65d87e
--- /dev/null
+++ b/fpga_interchange/examples/tests/lut_nexus/CMakeLists.txt
@@ -0,0 +1,10 @@
+add_interchange_test(
+    name lut_nexus
+    family ${family}
+    device LIFCL-17
+    package QFN72
+    tcl run.tcl
+    xdc empty.xdc
+    sources lut.v
+    skip_dcp
+)
diff --git a/fpga_interchange/examples/tests/lut_nexus/empty.xdc b/fpga_interchange/examples/tests/lut_nexus/empty.xdc
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/fpga_interchange/examples/tests/lut_nexus/empty.xdc
diff --git a/fpga_interchange/examples/tests/lut_nexus/lut.v b/fpga_interchange/examples/tests/lut_nexus/lut.v
new file mode 100644
index 00000000..5913aff1
--- /dev/null
+++ b/fpga_interchange/examples/tests/lut_nexus/lut.v
@@ -0,0 +1,7 @@
+module top;
+	wire x, y;
+	(*keep*)
+	LUT4 lut_0(.A(x), .B(x), .C(x), .D(x), .Z(y));
+	(*keep*)
+	LUT4 lut_1(.A(y), .B(y), .C(y), .D(y), .Z(x));
+endmodule
\ No newline at end of file
diff --git a/fpga_interchange/examples/tests/lut_nexus/run.tcl b/fpga_interchange/examples/tests/lut_nexus/run.tcl
new file mode 100644
index 00000000..4aa56c13
--- /dev/null
+++ b/fpga_interchange/examples/tests/lut_nexus/run.tcl
@@ -0,0 +1,14 @@
+yosys -import
+
+read_verilog $::env(SOURCES)
+
+synth_nexus -noccu2 -nobram -nolutram -nowidelut
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json $::env(OUT_JSON)
diff --git a/fpga_interchange/family.cmake b/fpga_interchange/family.cmake
index 139914ef..fdfa7004 100644
--- a/fpga_interchange/family.cmake
+++ b/fpga_interchange/family.cmake
@@ -8,6 +8,8 @@ find_package(ZLIB REQUIRED)
 set(RAPIDWRIGHT_PATH $ENV{HOME}/RapidWright CACHE PATH "Path to RapidWright")
 set(INVOKE_RAPIDWRIGHT "${RAPIDWRIGHT_PATH}/scripts/invoke_rapidwright.sh" CACHE PATH "Path to RapidWright invocation script")
 set(JAVA_HEAP_SPACE "-Xmx8g" CACHE STRING "Heap space reserved for Java")
+set(PRJOXIDE_PREFIX $ENV{HOME}/.cargo CACHE PATH "prjoxide install prefix")
+
 # FIXME: Make patch data available in the python package and remove this cached var
 set(PYTHON_INTERCHANGE_PATH $ENV{HOME}/python-fpga-interchange CACHE PATH "Path to the FPGA interchange python library")
 set(INTERCHANGE_SCHEMA_PATH ${PROJECT_SOURCE_DIR}/3rdparty/fpga-interchange-schema/interchange CACHE PATH "Path to the FPGA interchange schema dir")