iCE40/nextpnr - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	interchange: Reserve site ports only reachable from dedicated routing	gatecat	2021-07-01	1	-0/+2
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	interchange: add support for generating BEL clusters	Alessandro Comodi	2021-06-11	1	-5/+3
\| \| \| \| \| \| \| \|	Clustering greatly helps the placer to identify and pack together specific cells at the same site (e.g. LUT+FF), or cells that are chained through dedicated interconnections (e.g. CARRY CHAINS) Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
*	Using hashlib in arches	gatecat	2021-06-02	1	-1/+1
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	Initial version of inverter logic.	Keith Rothman	2021-03-23	1	-0/+16
\| \| \| \| \| \| \|	For now just implements some inspection capabilities, and the site router (for now) avoids inverted paths. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
*	Rework FPGA interchange site router.	Keith Rothman	2021-03-22	1	-0/+193
	The new site router should be robust to most situations, and isn't significantly slower with the use of caching. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>