aboutsummaryrefslogtreecommitdiffstats
path: root/fpga_interchange/site_router.cc
Commit message (Collapse)AuthorAgeFilesLines
* refactor: New member functions to replace design_utilsgatecat2022-02-181-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2021-09-061-2/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: entirely disable cache when binding site routingAlessandro Comodi2021-08-311-6/+6
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #757 from antmicro/lut-mapping-cachegatecat2021-07-221-25/+55
|\ | | | | interchange: Add caching of site LUT mapping solution
| * Added an option to disable the LUT mapping cacheMaciej Kurc2021-07-221-2/+5
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Added more code comments, formatted the codeMaciej Kurc2021-07-221-4/+1
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Working site LUT mapping cacheMaciej Kurc2021-07-161-26/+56
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | interchange: Fix preferred constant handling when canInvertgatecat2021-07-201-1/+10
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Handle canInvert PIPs when processing preferred constantsgatecat2021-07-011-5/+9
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Reserve site ports only reachable from dedicated routinggatecat2021-07-011-0/+59
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Cope with undriven nets in more placesgatecat2021-06-141-0/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: clusters: adjust commentsAlessandro Comodi2021-06-111-1/+4
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: add support for generating BEL clustersAlessandro Comodi2021-06-111-2/+44
| | | | | | | | Clustering greatly helps the placer to identify and pack together specific cells at the same site (e.g. LUT+FF), or cells that are chained through dedicated interconnections (e.g. CARRY CHAINS) Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Using hashlib in archesgatecat2021-06-021-14/+10
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: Don't error out on missing cell portsgatecat2021-05-211-2/+1
| | | | | | | This is required for LUTRAM support, as the upper address bits of RAMD64E etc are missing for shallower primitives. Signed-off-by: gatecat <gatecat@ds0.me>
* Run clangformatgatecat2021-05-161-3/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* interchange: pseudo pips: fix illegal tile pseudo PIPsAlessandro Comodi2021-05-141-6/+24
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: site router: add valid pips list to check during routingAlessandro Comodi2021-05-131-0/+43
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: site router: fix log messagesAlessandro Comodi2021-05-101-3/+3
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: site router: fix illegal site thru pathsAlessandro Comodi2021-05-101-0/+12
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Hash table refactoringgatecat2021-04-141-4/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2021-04-121-10/+12
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* [interchange] Fix invalid use of local variables due to refactoring.Keith Rothman2021-04-061-6/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Prevent site router from generating incorrect LUTs.Keith Rothman2021-04-061-34/+86
| | | | | | | | | The previous logic tied LUT input pins to VCC if a wire was unplacable. This missed a case where the net was present to the input of the LUT, but a wire was still not legal. This case is now prevented by tying the output of the LUT to an unused net. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [interchange] Add some documentation for the site router.Keith Rothman2021-04-051-10/+58
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* interchange: Fix bug in site router where a bad solution isn't remove.Keith Rothman2021-03-251-3/+7
| | | | | | | This resulted in valid site routing solutions being missed. Underlying bug was an off-by-one error when unwinding a failed solution. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Implement debugging tools for site router.Keith Rothman2021-03-251-13/+67
| | | | | | | | - Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire - Adds "explain_bel_status", which should be an exhaustive diagnostic of the status of a BEL placement. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial handling of local site inverters and constant signals.Keith Rothman2021-03-251-31/+294
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [FPGA interchange] Small fix to get_net_type.Keith Rothman2021-03-251-6/+6
| | | | | | | If get_net_type was called before the driver was placed, it could return the wrong value. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #640 from litghost/inversion_logicgatecat2021-03-231-8/+18
|\ | | | | Initial inverter logic for FPGA interchange
| * Initial version of inverter logic.Keith Rothman2021-03-231-8/+18
| | | | | | | | | | | | | | For now just implements some inspection capabilities, and the site router (for now) avoids inverted paths. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | interchange: Add nice error for missing cell pinsgatecat2021-03-231-0/+3
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Rework FPGA interchange site router.Keith Rothman2021-03-221-567/+528
| | | | | | | The new site router should be robust to most situations, and isn't significantly slower with the use of caching. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* For now just return false in the site router.Keith Rothman2021-02-261-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial LUT rotation logic.Keith Rothman2021-02-261-5/+30
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix assorted bugs in FPGA interchange.Keith Rothman2021-02-231-10/+76
| | | | | | | | | | Fixes: - Only use map constant pins during routing, and not during placement. - Unmapped cell ports have no BEL pins. - Fix SiteRouter congestion not taking into account initial expansion. - Fix psuedo-site pip output. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial logic for handling dedicated interconnect situations.Keith Rothman2021-02-231-0/+6
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Do some spell checking on site_router.ccKeith Rothman2021-02-181-18/+18
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add some utility methods for site instance access.Keith Rothman2021-02-181-6/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial site router.Keith Rothman2021-02-171-0/+753
This site router likely cannot handle the full problem space. It may need to be replaced with a more generalize approach as testing continues. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-01 02:29:37 +0000