| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Using hashlib in arches | gatecat | 2021-06-02 | 1 | -7/+7 |
| * | clangformat | gatecat | 2021-04-12 | 1 | -7/+4 |
| * | [interchange] Prevent site router from generating incorrect LUTs. | Keith Rothman | 2021-04-06 | 1 | -6/+12 |
| * | [interchange] Add crude pseudo pip model. | Keith Rothman | 2021-04-06 | 1 | -1/+41 |
| * | Add some FIXME's around VCC assumption in LUT logic. | Keith Rothman | 2021-03-25 | 1 | -0/+17 |
| * | Re-work LUT mapping logic to only put VCC pins when required. | Keith Rothman | 2021-03-25 | 1 | -5/+111 |
| * | Refactor header structures in FPGA interchange Arch. | Keith Rothman | 2021-03-19 | 1 | -1/+17 |
| * | Use NEXTPNR_NAMESPACE macro's now that headers are seperated. | Keith Rothman | 2021-03-15 | 1 | -1/+1 |
| * | clangformat | gatecat | 2021-03-03 | 1 | -92/+86 |
| * | Initial LUT rotation logic. | Keith Rothman | 2021-02-26 | 1 | -0/+370 |
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index : iCE40/nextpnr | |
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