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* Using hashlib in archesgatecat2021-06-0266-549/+358
* Use hashlib in routersgatecat2021-06-024-41/+37
* Bump tests submodulegatecat2021-06-021-0/+0
* Use hashlib in placersgatecat2021-06-027-52/+43
* Use hashlib for core netlist structuresgatecat2021-06-0249-368/+383
* Add hash() member functionsgatecat2021-06-029-7/+51
* common: Import hashlib from Yosysgatecat2021-06-022-0/+1184
* Merge pull request #719 from YosysHQ/gatecat/mistral-llvmgatecat2021-06-023-4/+4
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| * mistral: Fix nextpnr build with LLVMgatecat2021-06-023-4/+4
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* clangformatgatecat2021-06-011-1/+1
* Merge pull request #717 from YosysHQ/gatecat/timing-memory-fixgatecat2021-06-011-1/+1
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| * timing: Fix use of uninitialised valuegatecat2021-06-011-1/+1
* | Merge pull request #715 from YosysHQ/gatecat/ic-lifcl40gatecat2021-06-0112-4/+85
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| * interchange: Add LIFCL-40 EVN testsgatecat2021-06-0112-4/+85
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* Fixed warnings in QtPropertyBrowser componentMiodrag Milanovic2021-05-312-2/+0
* Fix hidpi, fixes #167, fixes #275, fixes #425Miodrag Milanovic2021-05-312-3/+10
* Merge pull request #714 from YosysHQ/gatecat/mistral-dis-compressgatecat2021-05-302-1/+9
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| * mistral: Make RBF compression optionalgatecat2021-05-302-1/+9
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* Merge pull request #713 from YosysHQ/gatecat/version-bumpgatecat2021-05-272-1/+1
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| * interchange: Bump versionsgatecat2021-05-272-1/+1
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* Merge pull request #686 from YosysHQ/gatecat/interchange-macrogatecat2021-05-2114-4/+414
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| * interchange: Bump versionsgatecat2021-05-212-1/+1
| * interchange: Add macro parameter mappinggatecat2021-05-212-3/+53
| * interchange: Don't error out on missing cell portsgatecat2021-05-212-2/+3
| * interchange: Add LUTRAM testgatecat2021-05-216-0/+169
| * interchange: Preliminary implementation of macro expansiongatecat2021-05-213-0/+116
| * interchange: Add macro param map rules to chipdbgatecat2021-05-211-0/+24
| * interchange: Add macro data to chipdbgatecat2021-05-211-1/+51
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* Merge pull request #712 from YosysHQ/gatecat/rr-heatmapgatecat2021-05-216-3/+64
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| * router2: Add heatmap by routing resource typegatecat2021-05-206-3/+64
* | Merge pull request #711 from acomodi/interchange-site-to-pseudo-pipsgatecat2021-05-203-4/+29
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| * gh-actions: interchange: use commit sha as cache keyAlessandro Comodi2021-05-201-4/+10
| * bump interchange schemaAlessandro Comodi2021-05-201-0/+0
| * interchange: phys: add site instance idstr for pseudo tile PIPsAlessandro Comodi2021-05-191-0/+19
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* Run clangformatgatecat2021-05-163-6/+8
* Merge pull request #708 from Ravenslofty/mistral-getchipnamegatecat2021-05-151-1/+1
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| * mistral: add getChipNameLofty2021-05-151-1/+1
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* Merge pull request #707 from gatecat/cyclonevgatecat2021-05-1531-9/+4222
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| * Update READMEgatecat2021-05-151-0/+1
| * mistral: Add MISTRAL_CLKBUF cell typegatecat2021-05-155-1/+15
| * ci: Use GH only for Mistral and fpga-interchangegatecat2021-05-153-2/+58
| * mistral: Tidying upgatecat2021-05-1512-12/+13
| * mistral: Make router2 the defaultgatecat2021-05-151-1/+1
| * router2: Hacky workaround for slow Cyclone V convergencegatecat2021-05-151-3/+3
| * mistral: Speed up bel binding and checkinggatecat2021-05-151-4/+18
| * mistral: Workaround for weird SCLR issuegatecat2021-05-151-0/+7
| * mistral: Fix ENA and ACLR bitstream generationgatecat2021-05-154-4/+11
| * mistral: Disable global buffers that are currently brokengatecat2021-05-151-0/+2
| * router2: Reduce verbosity when debugginggatecat2021-05-151-0/+2
| * mistral: Compensate for EF_SEL mirroring in validity checkgatecat2021-05-151-2/+2
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