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* Working FF example now that constant merging is done.Keith Rothman2021-02-231-5/+182
* Add initial logic for handling dedicated interconnect situations.Keith Rothman2021-02-231-0/+5
* Remove some signedness warnings.Keith Rothman2021-02-231-1/+1
* Add initial constant network support to FPGA interchange arch.Keith Rothman2021-02-231-1/+1
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-1/+1
* Add some utility methods for site instance access.Keith Rothman2021-02-181-2/+2
* Refactor "get only from iterator" to a utility.Keith Rothman2021-02-171-5/+2
* Change how package pin IO sites are selected.Keith Rothman2021-02-171-1/+17
* Continue fixes.Keith Rothman2021-02-171-0/+12
* Add initial site router.Keith Rothman2021-02-171-1/+1
* Working on standing up initial constraints system.Keith Rothman2021-02-171-11/+76
* clangformatgatecat2021-02-171-3/+4
* Require `--package` when arch BBA contains multiple packages.Keith Rothman2021-02-161-3/+11
* [FPGA Interchange] Add Cell -> BEL Pin maps.Keith Rothman2021-02-161-7/+161
* Add FPGA interchange frontend and backend.Keith Rothman2021-02-151-2/+19
* Run "make clangformat".Keith Rothman2021-02-121-5/+5
* Refactor XDC parser into a little class for testing purposes.Keith Rothman2021-02-121-0/+11
* Add FPGA interchange XDC parser.Keith Rothman2021-02-121-0/+7
* interchange: Base on ArchAPID. Shah2021-02-081-3/+1
* Add RelSlice::ssize and use it when comparing with signed ints.Keith Rothman2021-02-051-14/+14
* Move all string data into BBA file.Keith Rothman2021-02-051-8/+8
* Use RelSlice instead of RelPtr in cases where sizes are present.Keith Rothman2021-02-041-17/+17
* Update APIs to conform to style guide.Keith Rothman2021-02-041-10/+10
* Update copywrite headers.Keith Rothman2021-02-041-1/+2
* Fix warnings with signed/unsigned.Keith Rothman2021-02-041-1/+1
* Run "make clangformat".Keith Rothman2021-02-041-36/+23
* Update FPGA interchange to use IdStringList.Keith Rothman2021-02-041-100/+112
* Start adding data for placement constraint solving.Keith Rothman2021-02-041-45/+21
* Add initial updates to FPGA interchange arch for BEL buckets.Keith Rothman2021-02-041-0/+7
* Address review comments.Keith Rothman2021-02-041-8/+5
* Fix BBA import bugs.Keith Rothman2021-02-041-48/+155
* Assorted fixes to new FPGA interchange based arch.Keith Rothman2021-02-041-4/+12
* Initial compiling version.Keith Rothman2021-02-041-0/+9
* Initial FPGA interchange (which is just a cut-down xilinx arch).Keith Rothman2021-02-041-0/+474