| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Run "make clangformat". | Keith Rothman | 2021-02-02 | 1 | -2/+2 |
| * | Rename Partition -> BelBucket. | Keith Rothman | 2021-02-02 | 1 | -3/+3 |
| * | Working compile of ECP5. | Keith Rothman | 2021-02-02 | 1 | -1/+1 |
| * | Refactor ECP5 to new Partition API. | Keith Rothman | 2021-02-02 | 1 | -0/+13 |
| * | cleanup: Remove dead/unused code | D. Shah | 2021-01-28 | 1 | -25/+0 |
| * | ecp5: Switch from RelPtr to RelSlice | D. Shah | 2021-01-27 | 1 | -67/+53 |
| * | ecp5: Fix FF timing data | David Shah | 2020-12-17 | 1 | -4/+4 |
| * | Fix clangformat and execute it | Miodrag Milanovic | 2020-06-27 | 1 | -12/+8 |
| * | Simplify and improve chipdb embedding/loading. | whitequark | 2020-06-26 | 1 | -49/+33 |
| * | CMake: rewrite chipdb handling from ground up. | whitequark | 2020-06-25 | 1 | -2/+2 |
| * | Port nextpnr-{ice40,ecp5} to WASI. | whitequark | 2020-05-23 | 1 | -2/+3 |
| * | ecp5: MULT18X18D timing fixes | David Shah | 2020-05-01 | 1 | -10/+26 |
| * | No cell delay for clocked MULT18X18D | Ross Schlaikjer | 2020-04-30 | 1 | -0/+2 |
| * | Issue warning for mixed-mode inputs | Ross Schlaikjer | 2020-04-29 | 1 | -24/+11 |
| * | Handle register timing case | Ross Schlaikjer | 2020-04-29 | 1 | -6/+58 |
| * | Use registered port class on mult18x18 | Ross Schlaikjer | 2020-04-29 | 1 | -3/+5 |
| * | Alter MULT18X18D timing db based on register config | Ross Schlaikjer | 2020-04-28 | 1 | -1/+1 |
| * | Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-database | David Shah | 2020-04-07 | 1 | -4/+2 |
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| | * | Actually just move all the logic to ArchInfo | Ross Schlaikjer | 2020-04-07 | 1 | -15/+2 |
| | * | Extract regmode configuration to ArchInfo | Ross Schlaikjer | 2020-04-07 | 1 | -8/+4 |
| | * | Change timing database lookup based on REGMODE value | Ross Schlaikjer | 2020-04-07 | 1 | -4/+19 |
| * | | ecp5: Proper support for '12k' device | David Shah | 2020-03-13 | 1 | -2/+7 |
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| * | router2: Improve flow and log output | David Shah | 2020-02-03 | 1 | -1/+1 |
| * | Allow selection of router algorithm | David Shah | 2020-02-03 | 1 | -2/+16 |
| * | router2: Make magic numbers configurable | David Shah | 2020-02-03 | 1 | -1/+1 |
| * | ecp5: Improve bounding box accuracy | David Shah | 2020-02-03 | 1 | -4/+19 |
| * | ecp5: router2 main rename | David Shah | 2020-02-03 | 1 | -1/+1 |
| * | ecp5: Router2 test integration | David Shah | 2020-02-03 | 1 | -1/+38 |
| * | Merge remote-tracking branch 'origin/master' into mmicko/ecp5_gui | Miodrag Milanovic | 2019-12-28 | 1 | -1/+11 |
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| | * | ecp5: Add an error for out-of-sync constids and bba | David Shah | 2019-10-26 | 1 | -0/+3 |
| | * | ecp5: Fix routing to shared DSP control inputs | David Shah | 2019-10-25 | 1 | -1/+8 |
| * | | move bel creation to gfx.cc | Miodrag Milanovic | 2019-12-15 | 1 | -122/+2 |
| * | | fix formating | Miodrag Milanovic | 2019-12-14 | 1 | -2/+1 |
| * | | more new wires added | Miodrag Milanovic | 2019-12-14 | 1 | -1/+10 |
| * | | ebr, mult and alu nice display | Miodrag Milanovic | 2019-12-14 | 1 | -1/+1 |
| * | | clangformat run | Miodrag Milanovic | 2019-12-08 | 1 | -27/+30 |
| * | | display IOs properly | Miodrag Milanovic | 2019-12-07 | 1 | -21/+5 |
| * | | More bels show properly | Miodrag Milanovic | 2019-12-07 | 1 | -43/+82 |
| * | | add dcca bels and dummy parts for other bels | Miodrag Milanovic | 2019-12-07 | 1 | -9/+54 |
| * | | more pips, and valid mapping | Miodrag Milanovic | 2019-11-10 | 1 | -4/+4 |
| * | | Draw some pips, fixed H6 and V6 | Miodrag Milanovic | 2019-11-09 | 1 | -1/+22 |
| * | | Show V02/V06/H02/H06 | Miodrag Milanovic | 2019-10-25 | 1 | -1/+1 |
| * | | Split graphics calls for wires into gfx.cc | Miodrag Milanovic | 2019-10-20 | 1 | -268/+3 |
| * | | muxes only together with slices | Miodrag Milanovic | 2019-10-20 | 1 | -9/+7 |
| * | | Remove not used line | Miodrag Milanovic | 2019-10-20 | 1 | -2/+0 |
| * | | Simplify layout of elements | Miodrag Milanovic | 2019-10-20 | 1 | -170/+114 |
| * | | fix slice wire | Miodrag Milanovic | 2019-10-20 | 1 | -20/+20 |
| * | | bound signals | Miodrag Milanovic | 2019-10-20 | 1 | -0/+65 |
| * | | more wires between switchboxes | Miodrag Milanovic | 2019-10-20 | 1 | -1/+37 |
| * | | Add more types of wires | Miodrag Milanovic | 2019-10-20 | 1 | -176/+191 |
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index : iCE40/nextpnr | |
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