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| | * flush logs when throwing an assertion_failureClifford Wolf2018-11-101-0/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Add checkers and assertions to router1 and other improvementsClifford Wolf2018-11-102-42/+280
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Fixes and cleanups in router1Clifford Wolf2018-11-101-10/+10
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Fix log msg typoClifford Wolf2018-11-091-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Improve router console outputClifford Wolf2018-11-091-10/+13
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Fixes and improvements in new routerClifford Wolf2018-11-092-16/+57
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Essentially a rewrite router1Clifford Wolf2018-11-092-782/+341
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Merge branch 'master' of github.com:YosysHQ/nextpnr into router_improveClifford Wolf2018-11-0913-45/+255
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| | * | Dispose of far too long routes earlier (use 3x est. delay as limit)Clifford Wolf2018-09-041-12/+21
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Merge pull request #105 from YosysHQ/placer1_tmg_ignoreClifford Wolf2018-11-131-6/+6
| |\ \ \ | | | | | | | | | | [placer1] Ignore timing of TMG_IGNORE nets
| | * | | [placer1] Tidy up logicEddie Hung2018-11-131-3/+3
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| | * | | [placer1] Actually check for TMG_IGNORE!Eddie Hung2018-11-101-1/+1
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| | * | | [placer1] Ignore timing of TMG_IGNORE netsEddie Hung2018-11-101-5/+5
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* | | | timing: Fix compile warningDavid Shah2018-11-121-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | timing: Add support for clock constraintsDavid Shah2018-11-123-4/+35
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | ecp5: Update arch to new timing APIDavid Shah2018-11-121-2/+1
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | timing: Fix Fmax for clocks with mixed edge usageDavid Shah2018-11-121-10/+11
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | archapi: Add getDelayFromNS to improve timing algorithm portabilityDavid Shah2018-11-121-3/+3
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | timing: Fix handling of clock inputsDavid Shah2018-11-121-10/+17
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | timing: Don't include false startpoints in async pathsDavid Shah2018-11-121-2/+8
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | timing: Improve Fmax output and print cross-clock pathsDavid Shah2018-11-123-54/+132
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | timing: Multiple clock analysisDavid Shah2018-11-122-9/+31
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Working on multi-clock analysisDavid Shah2018-11-123-185/+272
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Working on adding multiple domains to timing analysisDavid Shah2018-11-121-33/+87
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | timing: Implementing parts of new timing APIDavid Shah2018-11-122-0/+96
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | | | timing: Working on a timing constraint APIDavid Shah2018-11-122-1/+105
|/ / / | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | | [timing] Fix combinational -> combinatorialEddie Hung2018-11-111-2/+2
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* | | [timing] Better messaging for failed timing analysis, allow --force toEddie Hung2018-11-111-1/+4
|/ / | | | | | | continue
* | [common] placer to produce error when >1 cell->bel constraintEddie Hung2018-11-081-0/+6
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* | gui: improved FPGAViewWidget::paintGL() performanceMateusz Zalega2018-10-231-0/+14
| | | | | | | | | | | | | | | | | | Profiling revealed that memcpy() in QOpenGLBuffer::allocate() had been taking the most time during paintGL() calls. I've been able to take the CPU usage down to about 1/4 of its previous values by caching elements in VBOs and updating them only after subsequent calls to renderGraphicElement(). Signed-off-by: Mateusz Zalega <mateusz@appliedsourcery.com>
* | Merge pull request #92 from YosysHQ/python-cmdlineDavid Shah2018-10-212-15/+41
|\ \ | | | | | | Allow running Python scripts for all points in flow
| * | common: Allow running Python scripts for all points in flowDavid Shah2018-10-172-15/+41
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Merge pull request #89 from YosysHQ/ecp5_bramDavid Shah2018-10-171-0/+6
|\ \ \ | |/ / |/| | ECP5 BRAM support
| * | placer: Fix conflicts during constraint legalisationDavid Shah2018-10-111-0/+6
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Merge pull request #88 from YosysHQ/issue72Eddie Hung2018-10-111-17/+6
|\ \ \ | |/ / |/| | Resolve issue #72
| * | [timing] Restore and skip false startpointsEddie Hung2018-09-151-17/+6
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* | clangformatDavid Shah2018-10-011-3/+1
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | ecp5: Debugging DRAM packingDavid Shah2018-10-012-0/+23
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | design_utils: Adding some design helper functionsDavid Shah2018-10-012-0/+36
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | ecp5: Helper functions for distributed RAM supportDavid Shah2018-10-011-0/+2
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Refactor chain finder to its own fileDavid Shah2018-09-302-1/+70
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | ecp5: Adding carry helper functionsDavid Shah2018-09-302-0/+22
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | clangformatDavid Shah2018-09-304-11/+19
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Merge pull request #81 from YosysHQ/ecp5_globalsDavid Shah2018-09-302-0/+13
|\ \ | | | | | | Adding a simple ECP5 global network router
| * | ecp5: Use ArchNetInfo to mark global nets to ignoreDavid Shah2018-09-292-7/+7
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | ecp5: Global router produces a working bitstreamDavid Shah2018-09-292-0/+13
| |/ | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* / Make warnings visible in quiet modeMiodrag Milanovic2018-09-191-2/+0
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* Merge pull request #66 from YosysHQ/issue65Serge Bazanski2018-08-261-4/+5
|\ | | | | Fix for min_slack == max_slack => bin_size == 0
| * Fix for min_slack == max_slack => bin_size == 0Eddie Hung2018-08-221-4/+5
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* | Merge pull request #47 from YosysHQ/settings_propagateClifford Wolf2018-08-188-14/+118
|\ \ | | | | | | Use settings for placer1 and router1
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