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author | Eddie Hung <eddieh@ece.ubc.ca> | 2018-11-11 13:49:09 -0800 |
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committer | Eddie Hung <eddieh@ece.ubc.ca> | 2018-11-11 13:49:09 -0800 |
commit | 7af788f9e3bbd08b815ff5b6aa087d80e5ab8a85 (patch) | |
tree | 52d40650d070bb6331f71e5c2fb5f615ca3cf90a /common | |
parent | 24380270208012a8e4eca9e3f8d21f45d4d3b739 (diff) | |
download | nextpnr-7af788f9e3bbd08b815ff5b6aa087d80e5ab8a85.tar.gz nextpnr-7af788f9e3bbd08b815ff5b6aa087d80e5ab8a85.tar.bz2 nextpnr-7af788f9e3bbd08b815ff5b6aa087d80e5ab8a85.zip |
[timing] Fix combinational -> combinatorial
Diffstat (limited to 'common')
-rw-r--r-- | common/timing.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/common/timing.cc b/common/timing.cc index 889880d4..2769cd65 100644 --- a/common/timing.cc +++ b/common/timing.cc @@ -167,9 +167,9 @@ struct Timing } } if (ctx->force) - log_warning("timing analysis failed due to presence of combinational loops, incomplete specification of timing ports, etc.\n"); + log_warning("timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc.\n"); else - log_error("timing analysis failed due to presence of combinational loops, incomplete specification of timing ports, etc.\n"); + log_error("timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc.\n"); } // Go forwards topographically to find the maximum arrival time and max path length for each net |