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| * | | | generic: Use arch_pybindings_sharedgatecat2022-07-042-105/+18
| | |/ / | |/| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | | Merge pull request #1002 from gsomlo/gls-pybind11-unbundlemyrtle2022-07-051-1/+6
|\ \ \ \ | |/ / / |/| | | Enable building against unbundled pybind11
| * | | Enable building against unbundled pybind11Gabriel Somlo2022-07-041-1/+6
|/ / / | | | | | | | | | Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
| | * gowin: fix compilationYRabbit2022-07-041-0/+1
| | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * gowin: Let the placer know about global networksYRabbit2022-07-045-259/+367
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor in order to detect networks that will be routed in a special mode earlier. This makes it possible to mark the source of such networks as a global buffer, thereby removing their influence on element placement. In addition, timing classes are set for some cells. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * Merge branch 'master' into clock-wipYRabbit2022-07-042-10/+11
| | |\ | |_|/ |/| |
* | | Merge pull request #1000 from YosysHQ/gatecat/fix-empty-portsmyrtle2022-06-261-9/+9
|\ \ \ | | | | | | | | ice40: Fix accidental creation of empty ports
| * | | ice40: Fix accidental creation of empty portsgatecat2022-06-251-9/+9
|/ / / | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #997 from Chandler-Kluser/mastermyrtle2022-06-231-1/+2
|\ \ \ | | | | | | | | Update README.md
| * | | Update README.mdChandler Klüser2022-06-221-1/+2
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| | * gowin: process the CLK ports of the ODDR[C] primitivesYRabbit2022-06-242-7/+9
| | | | | | | | | | | | | | | | | | Also removed the useless references. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * gowin: add a separate router for the clocksYRabbit2022-06-235-1/+392
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A simple router that takes advantage of the fact that in each cell with DFFs their CLK inputs can directly connect to the global clock network. Networks with a large number of such sinks are sought and then each network is assigned to the available independent global clock networks. There are limited possibilities for routing mixed networks, that is, when the sinks are not only CLKs: in this case an attempt is made to use wires such as SN10/20 and EW10/20, that is, one short transition can be added between the global clock network and the sink. * At this time, networks with a source other than the I/O pin are not supported. This is typical for Tangnano4k and runber boards. * Router is disabled by default, you need to specify option --enable-globals to activate * No new chip bases are required. This may change in the distant future. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Disable broken and failing interchange CIgatecat2022-06-211-0/+0
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | clangformatgatecat2022-06-121-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | ecp5: Bind write_bitstream to Pythongatecat2022-06-091-0/+3
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #996 from yrabbit/snmyrtle2022-06-091-7/+11
|\ \ | | | | | | gowin: Use local aliases
| * | gowin: Use local aliasesYRabbit2022-06-091-7/+11
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the Gowin chips, the tiles are connected to each other by a one-hop wire, among others. There are 4 one-hop wires, of which 2 are shared between north/south and east/west, have three names: e.g. SN10 and N110 and S110. But only one of them, the first, occurs as a sink for PIP, that is, you can not get a route that would pass through the S110 for example. This commit corrects the names to SN?0 and EW?0 at the wire creation stage to avoid dead wires. In addition, the SN?0 and EW?0 are among the few sinks for global clock wires and now there is the possibility of a more optimal clock routing. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #993 from yrabbit/lw-wip-1myrtle2022-06-075-8/+299
|\ \ | |/ |/| gowin: Add support for long wires
| * gowin: Add support for long wiresYRabbit2022-05-275-8/+299
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Gowin chips have a highly sophisticated system of long wires that are wired to each cell and allow the clock or logic to spread quickly. This commit implements some of the capabilities of the long wire system for quadrants, leaving out the fine-tuning of them for each column. To make use of the long wire system, the specified wire is cut at the driver and a special cell is placed between the driver and the rest of the wire. * VCC and GND can not use long wires because they are in every cell and there is no point in using a net * Long wire numbers can be specified manually or assigned automatically. * The route from the driver to the port of the new cell can be quite long, this will have to be solved somehow. * It might make sense to add a mechanism for automatically finding candidates for long wires. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #992 from antmicro/mdudek/nexus_write_dccmyrtle2022-05-271-3/+2
|\ \ | | | | | | Change write_dcc to work with tilegroups from prjoxide
| * | Change write_dcc to work with tilegroups from prjoxideMaciej Dudek2022-05-271-3/+2
| |/ | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* | Merge pull request #990 from YosysHQ/gatecat/fix-988myrtle2022-05-221-5/+0
|\ \ | | | | | | Don't assert on mixed domain paths in report
| * | Don't assert on mixed domain paths in reportgatecat2022-05-221-5/+0
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #989 from YosysHQ/lofty/cmake-bumpmyrtle2022-05-211-1/+1
|\ \ | |/ |/| Bump minimum CMake to 3.13
| * Bump minimum CMake to 3.13Lofty2022-05-211-1/+1
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* Merge pull request #985 from antmicro/interchange-lut-constantsmyrtle2022-05-135-58/+180
|\ | | | | [interchange] Tying unused LUT inputs according to architecture
| * Added fallback to VCC as the preferred constant if the architecture does not ↵Maciej Kurc2022-05-123-6/+20
| | | | | | | | | | | | specify one. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Added tying unused LUT pins to preferred constant instead of VccMaciej Kurc2022-05-111-2/+8
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Generalized representation of unused LUT pins connectionsMaciej Kurc2022-05-115-58/+160
|/ | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* Merge pull request #984 from yrabbit/assertmyrtle2022-05-101-1/+1
|\ | | | | common: Correct a minor typo in the message
| * common: Correct a minor typo in the messageYRabbit2022-05-101-1/+1
|/ | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #982 from YosysHQ/gatecat/ice40-gb-constr-fixmyrtle2022-05-081-7/+24
|\ | | | | ice40: Fix propagation of constraints through SB_GB
| * ice40: Fix propagation of constraints through SB_GBgatecat2022-05-081-7/+24
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #981 from yrabbit/lw-cst-0gatecat2022-05-031-7/+27
|\ | | | | gowin: Add initial syntax support for long wires
| * gowin: Add initial syntax support for long wiresYRabbit2022-05-021-7/+27
| | | | | | | | | | | | | | Only the recognition of the directive in the .CST file and elementary checks are added, but not the long-wire mechanism itself. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | generic: Add some extra helpers for viaduct uarchesgatecat2022-05-024-4/+52
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* generic: Add missing uarch guardgatecat2022-04-271-1/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Tweak delay predictiongatecat2022-04-201-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #977 from YosysHQ/gatecat/prefine-tileswapgatecat2022-04-192-1/+100
|\ | | | | prefine: Do full-tile swaps, too
| * prefine: Do full-tile swaps, toogatecat2022-04-192-1/+100
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #976 from YosysHQ/gatecat/dp-reworkgatecat2022-04-175-545/+730
|\ | | | | Move general parallel detail place code out of parallel_refine
| * Move general parallel detail place code out of parallel_refinegatecat2022-04-175-545/+730
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #975 from YosysHQ/gatecat/ice40-carry-i3-fixgatecat2022-04-121-34/+45
|\ | | | | ice40: Avoid chain finder from mixing up chains by only allowing I3 c…
| * ice40: Avoid chain finder from mixing up chains by only allowing I3 chaining ↵gatecat2022-04-111-34/+45
|/ | | | | | at end Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #974 from YosysHQ/gatecat/ci-restructuregatecat2022-04-0816-125/+301
|\ | | | | ci: Restructure and move entirely to GH actions from Cirrus
| * ci: Restructure and move entirely to GH actions from Cirrusgatecat2022-04-0816-125/+301
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #973 from YosysHQ/gatecat/folder-tidygatecat2022-04-0875-3/+6
|\| | | | | Split up common into kernel,place,route
| * Split up common into kernel,place,routegatecat2022-04-0875-3/+6
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #972 from YosysHQ/gatecat/ecp5-split-slice-v2gatecat2022-04-0713-1349/+1137
|\ | | | | ecp5: Split the SLICE bel into separate LUT/FF/RAMW bels
| * ecp5: Split the SLICE bel into separate LUT/FF/RAMW belsgatecat2022-04-0713-1349/+1137
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