aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authormyrtle <gatecat@ds0.me>2022-05-27 10:13:15 +0100
committerGitHub <noreply@github.com>2022-05-27 10:13:15 +0100
commit997af6d7202b08c457c56db958c5e39605e74295 (patch)
tree253ee3a6e00013881e4e04f87e80ff103929e7ee
parent48f9daf867be56ffae9197adf18393786a4515c5 (diff)
parent8c4e3e91ccd7fc5c994f05e67a4605290d72079e (diff)
downloadnextpnr-997af6d7202b08c457c56db958c5e39605e74295.tar.gz
nextpnr-997af6d7202b08c457c56db958c5e39605e74295.tar.bz2
nextpnr-997af6d7202b08c457c56db958c5e39605e74295.zip
Merge pull request #992 from antmicro/mdudek/nexus_write_dcc
Change write_dcc to work with tilegroups from prjoxide
-rw-r--r--nexus/fasm.cc5
1 files changed, 2 insertions, 3 deletions
diff --git a/nexus/fasm.cc b/nexus/fasm.cc
index 3ed5785e..de03fb82 100644
--- a/nexus/fasm.cc
+++ b/nexus/fasm.cc
@@ -533,11 +533,10 @@ struct NexusFasmWriter
void write_dcc(const CellInfo *cell)
{
BelId bel = cell->bel;
- push_tile(bel.tile);
- push_belname(bel);
+ push_bel(bel);
write_bit("DCCEN.1"); // Explicit DCC cell implies a clock buffer
write_cell_muxes(cell);
- pop(2);
+ pop();
}
// Write config for DCS
void write_dcs(const CellInfo *cell)