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* ecp5: Fix packing of IOFF with IODELAYsgatecat2021-11-052-3/+11
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #855 from galibert/mastergatecat2021-10-282-4/+3
|\ | | | | mistral: Sync with yet another reorganization
| * mistral: Sync with yet another reorganizationOlivier Galibert2021-10-282-4/+3
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* Merge pull request #852 from yrabbit/pr-gowin-alugatecat2021-10-223-6/+226
|\ | | | | gowin: Add ALU support.
| * gowin: Explicitly initialize the y in the clusterYRabbit2021-10-221-0/+5
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: Add ALU support.YRabbit2021-10-223-6/+221
|/ | | | | | | | - Both the mode used by yosys and all Gowin primitive modes are supported. - The ALU always starts with a zero slice. - The maximum length of the ALU chain is limited to one line of the chip. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* interchange: Bump prjoxide versiongatecat2021-10-201-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #851 from galibert/mastergatecat2021-10-193-13/+14
|\ | | | | mistral: Use the iterators
| * Normalize formattingOlivier Galibert2021-10-192-13/+17
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| * mistral: Use the iteratorsOlivier Galibert2021-10-192-12/+9
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* Merge pull request #848 from galibert/mastergatecat2021-10-172-1/+2
|\ | | | | mistral: Support the new routes-to-bin intermediate tool generation
| * Sync mistral version in CIOlivier Galibert2021-10-171-1/+1
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| * mistral: Support the new routes-to-bin intermediate tool generationOlivier Galibert2021-10-171-0/+1
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* | Merge pull request #849 from galibert/cyclonev-oscillatorgatecat2021-10-174-3/+15
|\ \ | |/ |/| mistral: Add internal oscillator support
| * mistral: Add internal oscillator supportOlivier Galibert2021-10-174-3/+15
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* Merge pull request #847 from galibert/mastergatecat2021-10-154-0/+17
|\ | | | | mistral: Add support for cyclonev_hps_interface_mpu_general_purpose
| * cyclonev_hps_interface_mpu_general_purpose: Use a id_ identifierOlivier Galibert2021-10-152-1/+3
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| * mistral: Add support for cyclonev_hps_interface_mpu_general_purposeOlivier Galibert2021-10-143-0/+15
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* Merge pull request #845 from YosysHQ/gatecat/mlab-cluster-fixgatecat2021-10-112-2/+9
|\ | | | | mistral: Fix MLAB clustering
| * mistral: Fix MLAB clusteringgatecat2021-10-112-2/+9
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2021-10-112-29/+42
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #843 from Ravenslofty/lofty/mistral-basic-timinggatecat2021-10-113-21/+256
|\ | | | | mistral: very basic timing info
| * mistral: very basic timing infoLofty2021-10-104-22/+257
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* | Merge pull request #844 from pepijndevos/patch-2gatecat2021-10-101-2/+2
|\ \ | | | | | | Gowin: more clearly mark dummy pips
| * | Gowin: more clearly mark dummy pipsPepijn de Vos2021-10-101-2/+2
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* | Merge pull request #842 from yrabbit/delaysgatecat2021-10-093-12/+40
|\ \ | | | | | | gowin: Replace the zero delays with reasonable values.
| * \ Merge branch 'master' into delaysYRabbit2021-10-091-18/+6
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| * | | gowin: Replace the zero delays with reasonable values.YRabbit2021-10-093-12/+40
| | |/ | |/| | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | | router2: Disable criticality sorting towards end of routinggatecat2021-10-091-1/+1
| |/ |/| | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #841 from Ravenslofty/lofty/mistral-cleanupgatecat2021-10-081-18/+6
|\ \ | |/ |/| mistral: clean up bel init slightly
| * mistral: clean up bel init slightlyLofty2021-10-081-18/+6
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* hashlib: Support for std::array keysgatecat2021-10-071-0/+13
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #839 from yrabbit/wide-lutsgatecat2021-10-077-9/+434
|\ | | | | gowin: add support for wide LUTs.
| * gowin: add support for wide LUTs.YRabbit2021-10-077-9/+434
|/ | | | | | | | | * A hardwired MUX within each logical cell is used. * The delay is equal 0. * No user placement constraints. * The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #837 from YosysHQ/gatecat/mistral-mlab-2gatecat2021-10-058-21/+235
|\ | | | | mistral: Adding support for MLABs as memory
| * mistral: Adding support for MLABs as memorygatecat2021-10-058-21/+235
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #836 from YosysHQ/gatecat/mistral-mlabgatecat2021-10-032-19/+38
|\| | | | | mistral: Add bel pins for MLAB write port
| * mistral: Add bel pins for MLAB write portgatecat2021-10-032-19/+38
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #834 from YosysHQ/gatecat/cygwingatecat2021-10-011-1/+1
|\ | | | | Fix Cygwin build
| * Fix Cygwin buildgatecat2021-10-011-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #833 from antmicro/interchange-fix-uninitialized-memory-buggatecat2021-10-011-1/+1
|\ \ | |/ |/| interchange: fix uninitialized memory bug in cluster placement
| * interchange: fix uninitialized memory bug in cluster placementAlessandro Comodi2021-10-011-1/+1
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #828 from YosysHQ/gatecat/interchange-warn-fixgatecat2021-09-303-7/+10
|\ | | | | interchange: Enable Werror on CI and fix some compile warnings
| * interchange: Fix compile warningsgatecat2021-09-282-6/+9
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * ci: Enable -Werror for interchange archgatecat2021-09-281-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #810 from antmicro/write-timing-reportgatecat2021-09-297-158/+539
|\ \ | | | | | | Timing report in JSON format
| * | Code formattingMaciej Kurc2021-09-294-119/+87
| | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | Brought back printout of critical path source file references, added ↵Maciej Kurc2021-09-293-28/+74
| | | | | | | | | | | | | | | | | | clk-to-q, source and setup segment types Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | Shifted moving of data containers after printingMaciej Kurc2021-09-281-11/+11
| | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * | Added a commandline option controlled writeout of per-net timing detailsMaciej Kurc2021-09-284-9/+22
| | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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