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authorMaciej Kurc <mkurc@antmicro.com>2021-09-29 10:16:45 +0200
committerMaciej Kurc <mkurc@antmicro.com>2021-09-29 10:16:45 +0200
commit76f5874ffcd57f69808e0df752622dfe13759538 (patch)
tree6867d16a4c338fd1b734a13a4e392ea7659dee35
parent1ed692aca90a9a103fc5e15aeeae31b515072035 (diff)
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Brought back printout of critical path source file references, added clk-to-q, source and setup segment types
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
-rw-r--r--common/nextpnr_types.h7
-rw-r--r--common/report.cc13
-rw-r--r--common/timing.cc82
3 files changed, 74 insertions, 28 deletions
diff --git a/common/nextpnr_types.h b/common/nextpnr_types.h
index 17261095..8b19595b 100644
--- a/common/nextpnr_types.h
+++ b/common/nextpnr_types.h
@@ -246,8 +246,11 @@ struct CriticalPath
// Segment type
enum class Type {
- LOGIC,
- ROUTING
+ CLK_TO_Q, // Clock-to-Q delay
+ SOURCE, // Delayless source
+ LOGIC, // Combinational logic delay
+ ROUTING, // Routing delay
+ SETUP // Setup time in sink
};
// Type
diff --git a/common/report.cc b/common/report.cc
index f2926c86..1338ade5 100644
--- a/common/report.cc
+++ b/common/report.cc
@@ -82,9 +82,18 @@ static Json::array report_critical_paths (const Context* ctx) {
{"to", toJson},
});
- if (segment.type == CriticalPath::Segment::Type::LOGIC) {
+ if (segment.type == CriticalPath::Segment::Type::CLK_TO_Q) {
+ segmentJson["type"] = "clk-to-q";
+ }
+ else if (segment.type == CriticalPath::Segment::Type::SOURCE) {
+ segmentJson["type"] = "source";
+ }
+ else if (segment.type == CriticalPath::Segment::Type::LOGIC) {
segmentJson["type"] = "logic";
}
+ else if (segment.type == CriticalPath::Segment::Type::SETUP) {
+ segmentJson["type"] = "setup";
+ }
else if (segment.type == CriticalPath::Segment::Type::ROUTING) {
segmentJson["type"] = "routing";
segmentJson["net"] = segment.net.c_str(ctx);
@@ -201,7 +210,7 @@ Report JSON structure:
<grid y>
]
},
- "type": <path segment type "logic" or "routing">,
+ "type": <path segment type "clk-to-q", "source", "logic", "routing" or "setup">,
"net": <net name (for routing only!)>,
"delay": <segment delay [ns]>,
"budget": <segment delay budget [ns] (for routing only!)>,
diff --git a/common/timing.cc b/common/timing.cc
index b6d9b325..41dd358b 100644
--- a/common/timing.cc
+++ b/common/timing.cc
@@ -1143,20 +1143,24 @@ CriticalPath build_critical_path_report(Context* ctx, ClockPair &clocks, const P
auto net = port.net;
auto &driver = net->driver;
auto driver_cell = driver.cell;
+
+ CriticalPath::Segment seg_logic;
+
DelayQuad comb_delay;
if (clock_start != -1) {
auto clockInfo = ctx->getPortClockingInfo(driver_cell, driver.port, clock_start);
comb_delay = clockInfo.clockToQ;
clock_start = -1;
+ seg_logic.type = CriticalPath::Segment::Type::CLK_TO_Q;
} else if (last_port == driver.port) {
// Case where we start with a STARTPOINT etc
comb_delay = DelayQuad(0);
+ seg_logic.type = CriticalPath::Segment::Type::SOURCE;
} else {
ctx->getCellDelay(driver_cell, last_port, driver.port, comb_delay);
+ seg_logic.type = CriticalPath::Segment::Type::LOGIC;
}
- CriticalPath::Segment seg_logic;
- seg_logic.type = CriticalPath::Segment::Type::LOGIC;
seg_logic.delay = comb_delay.maxDelay();
seg_logic.budget = 0;
seg_logic.from = std::make_pair(last_cell->name, last_port);
@@ -1186,7 +1190,7 @@ CriticalPath build_critical_path_report(Context* ctx, ClockPair &clocks, const P
delay_t setup = sinkClockInfo.setup.maxDelay();
CriticalPath::Segment seg_logic;
- seg_logic.type = CriticalPath::Segment::Type::LOGIC;
+ seg_logic.type = CriticalPath::Segment::Type::SETUP;
seg_logic.delay = setup;
seg_logic.budget = 0;
seg_logic.from = std::make_pair(last_cell->name, last_port);
@@ -1302,6 +1306,33 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
// Print critical paths
if (print_path) {
+ static auto print_net_source = [ctx](const NetInfo *net) {
+ // Check if this net is annotated with a source list
+ auto sources = net->attrs.find(ctx->id("src"));
+ if (sources == net->attrs.end()) {
+ // No sources for this net, can't print anything
+ return;
+ }
+
+ // Sources are separated by pipe characters.
+ // There is no guaranteed ordering on sources, so we just print all
+ auto sourcelist = sources->second.as_string();
+ std::vector<std::string> source_entries;
+ size_t current = 0, prev = 0;
+ while ((current = sourcelist.find("|", prev)) != std::string::npos) {
+ source_entries.emplace_back(sourcelist.substr(prev, current - prev));
+ prev = current + 1;
+ }
+ // Ensure we emplace the final entry
+ source_entries.emplace_back(sourcelist.substr(prev, current - prev));
+
+ // Iterate and print our source list at the correct indentation level
+ log_info(" Defined in:\n");
+ for (auto entry : source_entries) {
+ log_info(" %s\n", entry.c_str());
+ }
+ };
+
// A helper function for reporting one critical path
auto print_path_report = [ctx](const CriticalPath& path) {
delay_t total = 0, logic_total = 0, route_total = 0;
@@ -1311,27 +1342,26 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
total += segment.delay;
- if (segment.type == CriticalPath::Segment::Type::LOGIC) {
+ if (segment.type == CriticalPath::Segment::Type::CLK_TO_Q ||
+ segment.type == CriticalPath::Segment::Type::SOURCE ||
+ segment.type == CriticalPath::Segment::Type::LOGIC ||
+ segment.type == CriticalPath::Segment::Type::SETUP)
+ {
logic_total += segment.delay;
- if (segment.from != segment.to) {
- log_info("%4.1f %4.1f Source %s.%s\n",
- ctx->getDelayNS(segment.delay),
- ctx->getDelayNS(total),
- segment.from.first.c_str(ctx),
- segment.from.second.c_str(ctx)
- );
- }
- else {
- log_info("%4.1f %4.1f Setup %s.%s\n",
- ctx->getDelayNS(segment.delay),
- ctx->getDelayNS(total),
- segment.to.first.c_str(ctx),
- segment.to.second.c_str(ctx)
- );
- }
- }
- if (segment.type == CriticalPath::Segment::Type::ROUTING) {
+ const std::string type_name =
+ (segment.type == CriticalPath::Segment::Type::SETUP) ?
+ "Setup" : "Source";
+
+ log_info("%4.1f %4.1f %s %s.%s\n",
+ ctx->getDelayNS(segment.delay),
+ ctx->getDelayNS(total),
+ type_name.c_str(),
+ segment.to.first.c_str(ctx),
+ segment.to.second.c_str(ctx)
+ );
+ }
+ else if (segment.type == CriticalPath::Segment::Type::ROUTING) {
route_total += segment.delay;
const auto& driver = ctx->cells.at(segment.from.first);
@@ -1352,6 +1382,8 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
segment.to.second.c_str(ctx)
);
+ const NetInfo* net = ctx->nets.at(segment.net).get();
+
if (ctx->verbose) {
PortRef sink_ref;
@@ -1359,8 +1391,6 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
sink_ref.port = segment.to.second;
sink_ref.budget = segment.budget;
- const NetInfo* net = ctx->nets.at(segment.net).get();
-
auto driver_wire = ctx->getNetinfoSourceWire(net);
auto sink_wire = ctx->getNetinfoSinkWire(net, sink_ref, 0);
log_info(" prediction: %f ns estimate: %f ns\n",
@@ -1382,6 +1412,10 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
cursor = ctx->getPipSrcWire(pip);
}
}
+
+ if (!ctx->disable_critical_path_source_print) {
+ print_net_source(net);
+ }
}
}
log_info("%.1f ns logic, %.1f ns routing\n", ctx->getDelayNS(logic_total), ctx->getDelayNS(route_total));