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* Merge pull request #1013 from YosysHQ/gatecat/viaduct-argsmyrtle2022-08-151-0/+14
|\ | | | | viaduct: Allow passing command line options to uarch with -o
| * viaduct: Allow passing command line options to uarch with -ogatecat2022-08-151-0/+14
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1012 from YosysHQ/gatecat/refactor-id-inmyrtle2022-08-1124-203/+153
|\ | | | | refactor: Use IdString::in instead of || chains
| * refactor: Use IdString::in instead of || chainsgatecat2022-08-1024-203/+153
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1011 from YosysHQ/gatecat/nexus-lram-tmgmyrtle2022-08-103-0/+30
|\ | | | | nexus: Add timing data for LRAM
| * nexus: Add timing data for LRAMgatecat2022-08-103-0/+30
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1010 from YosysHQ/gatecat/idfmyrtle2022-08-1022-153/+152
|\ | | | | refactor: id(stringf(...)) to new idf(...) helper
| * refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-1022-153/+152
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1008 from YosysHQ/gatecat/generic-addbelpinmyrtle2022-08-043-25/+12
|\ | | | | generic: addBelPin with direction as an arg
| * generic: addBelPin with direction as an arggatecat2022-08-043-25/+12
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1004 from yrabbit/fix-muxesmyrtle2022-07-217-38/+26
|\ | | | | gowin: Remove incomprehensible names of the muxes
| * Merge branch 'master' into fix-muxesYRabbit2022-07-201-1/+1
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* | Merge pull request #1005 from YosysHQ/gatecat/nexus-ram-fixesmyrtle2022-07-191-1/+1
|\ \ | | | | | | nexus: Fix CSDECODE parsing
| * | nexus: Fix CSDECODE parsinggatecat2022-07-191-1/+1
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * gowin: fix compilationYRabbit2022-07-191-8/+0
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: Remove incomprehensible names of the muxesYRabbit2022-07-197-34/+30
|/ | | | | | | | | | | | There is no need to multiply item names, it is a rudiment of my very first addition to nextpnr. Fully compatible with older versions of Apicula. Note: the cosmetic changes in lines with RAM are not my initiative, but the result of applying clang-format. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #998 from yrabbit/clock-wipmyrtle2022-07-186-1/+479
|\ | | | | gowin: add a separate router for the clocks
| * Merge branch 'master' into clock-wipYRabbit2022-07-1016-49/+198
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* | Merge pull request #999 from YosysHQ/gatecat/pseudocell-apimyrtle2022-07-0816-49/+198
|\ \ | | | | | | netlist: Add PseudoCell API
| * | netlist: Add PseudoCell APIgatecat2022-07-0816-49/+198
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | When implementing concepts such as partition pins or deliberately split nets, there's a need for something that looks like a cell (starts/ends routing with pins on nets, has timing data) but isn't mapped to a fixed bel in the architecture, but instead can have pin mappings defined at runtime. The PseudoCell allows this by providing an alternate, virtual-function based API for such cells. When a cell has `pseudo_cell` used, instead of calling functions such as getBelPinWire, getBelLocation or getCellDelay in the Arch API; such data is provided by the cell itself, fully flexible at runtime regardless of arch, via methods on the PseudoCell implementation.
| * gowin: Remove unnecessary functionsYRabbit2022-07-052-33/+9
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * Merge branch 'master' into clock-wipYRabbit2022-07-059-106/+211
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* | Merge pull request #995 from pepijndevos/shadowrammyrtle2022-07-056-0/+187
|\ \ | | | | | | Gowin: WIP shadowram
| * | use DFF RAM modePepijn de Vos2022-07-021-1/+4
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| * | Merge branch 'master' into shadowramPepijn de Vos2022-07-029-25/+324
| |\ \
| * | | hook up CE maybePepijn de Vos2022-06-163-0/+4
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| * | | lutram actually PnRsPepijn de Vos2022-06-065-38/+43
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| * | | WIP shadowramPepijn de Vos2022-06-056-0/+175
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* | | | Merge pull request #1001 from YosysHQ/gatecat/generic-shared-pybmyrtle2022-07-052-105/+18
|\ \ \ \ | | | | | | | | | | generic: Use arch_pybindings_shared
| * | | | generic: Use arch_pybindings_sharedgatecat2022-07-042-105/+18
| | |/ / | |/| | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | | Merge pull request #1002 from gsomlo/gls-pybind11-unbundlemyrtle2022-07-051-1/+6
|\ \ \ \ | |/ / / |/| | | Enable building against unbundled pybind11
| * | | Enable building against unbundled pybind11Gabriel Somlo2022-07-041-1/+6
|/ / / | | | | | | | | | Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
| | * gowin: fix compilationYRabbit2022-07-041-0/+1
| | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * gowin: Let the placer know about global networksYRabbit2022-07-045-259/+367
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor in order to detect networks that will be routed in a special mode earlier. This makes it possible to mark the source of such networks as a global buffer, thereby removing their influence on element placement. In addition, timing classes are set for some cells. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * Merge branch 'master' into clock-wipYRabbit2022-07-042-10/+11
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* | | Merge pull request #1000 from YosysHQ/gatecat/fix-empty-portsmyrtle2022-06-261-9/+9
|\ \ \ | | | | | | | | ice40: Fix accidental creation of empty ports
| * | | ice40: Fix accidental creation of empty portsgatecat2022-06-251-9/+9
|/ / / | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #997 from Chandler-Kluser/mastermyrtle2022-06-231-1/+2
|\ \ \ | | | | | | | | Update README.md
| * | | Update README.mdChandler Klüser2022-06-221-1/+2
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| | * gowin: process the CLK ports of the ODDR[C] primitivesYRabbit2022-06-242-7/+9
| | | | | | | | | | | | | | | | | | Also removed the useless references. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| | * gowin: add a separate router for the clocksYRabbit2022-06-235-1/+392
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A simple router that takes advantage of the fact that in each cell with DFFs their CLK inputs can directly connect to the global clock network. Networks with a large number of such sinks are sought and then each network is assigned to the available independent global clock networks. There are limited possibilities for routing mixed networks, that is, when the sinks are not only CLKs: in this case an attempt is made to use wires such as SN10/20 and EW10/20, that is, one short transition can be added between the global clock network and the sink. * At this time, networks with a source other than the I/O pin are not supported. This is typical for Tangnano4k and runber boards. * Router is disabled by default, you need to specify option --enable-globals to activate * No new chip bases are required. This may change in the distant future. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Disable broken and failing interchange CIgatecat2022-06-211-0/+0
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | clangformatgatecat2022-06-121-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | ecp5: Bind write_bitstream to Pythongatecat2022-06-091-0/+3
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #996 from yrabbit/snmyrtle2022-06-091-7/+11
|\ \ | | | | | | gowin: Use local aliases
| * | gowin: Use local aliasesYRabbit2022-06-091-7/+11
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the Gowin chips, the tiles are connected to each other by a one-hop wire, among others. There are 4 one-hop wires, of which 2 are shared between north/south and east/west, have three names: e.g. SN10 and N110 and S110. But only one of them, the first, occurs as a sink for PIP, that is, you can not get a route that would pass through the S110 for example. This commit corrects the names to SN?0 and EW?0 at the wire creation stage to avoid dead wires. In addition, the SN?0 and EW?0 are among the few sinks for global clock wires and now there is the possibility of a more optimal clock routing. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #993 from yrabbit/lw-wip-1myrtle2022-06-075-8/+299
|\ \ | |/ |/| gowin: Add support for long wires
| * gowin: Add support for long wiresYRabbit2022-05-275-8/+299
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Gowin chips have a highly sophisticated system of long wires that are wired to each cell and allow the clock or logic to spread quickly. This commit implements some of the capabilities of the long wire system for quadrants, leaving out the fine-tuning of them for each column. To make use of the long wire system, the specified wire is cut at the driver and a special cell is placed between the driver and the rest of the wire. * VCC and GND can not use long wires because they are in every cell and there is no point in using a net * Long wire numbers can be specified manually or assigned automatically. * The route from the driver to the port of the new cell can be quite long, this will have to be solved somehow. * It might make sense to add a mechanism for automatically finding candidates for long wires. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #992 from antmicro/mdudek/nexus_write_dccmyrtle2022-05-271-3/+2
|\ \ | | | | | | Change write_dcc to work with tilegroups from prjoxide
| * | Change write_dcc to work with tilegroups from prjoxideMaciej Dudek2022-05-271-3/+2
| |/ | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 03:47:22 +0000