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* mistral: Make router2 the defaultgatecat2021-05-151-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* router2: Hacky workaround for slow Cyclone V convergencegatecat2021-05-151-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Speed up bel binding and checkinggatecat2021-05-151-4/+18
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Workaround for weird SCLR issuegatecat2021-05-151-0/+7
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Fix ENA and ACLR bitstream generationgatecat2021-05-154-4/+11
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Disable global buffers that are currently brokengatecat2021-05-151-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* router2: Reduce verbosity when debugginggatecat2021-05-151-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Compensate for EF_SEL mirroring in validity checkgatecat2021-05-151-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Fix EF_SEL and BTO_DISgatecat2021-05-152-4/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: PKREG bits appear to be mirrored within a half?gatecat2021-05-151-2/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Debugging flipflopsgatecat2021-05-151-3/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Trim SDATA if SLOAD is lowgatecat2021-05-151-0/+9
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: FF&CLKBUF fixes, part 1gatecat2021-05-152-1/+10
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: First pass at FF and CLKBUF bitgengatecat2021-05-152-18/+115
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Account for TD input count limitgatecat2021-05-154-9/+128
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* msitral: Fix pip iterator Python bindingsgatecat2021-05-151-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Implement PIP locations, toogatecat2021-05-151-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Implement bounding boxes for router2gatecat2021-05-152-1/+15
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Debugging carry chain issuesgatecat2021-05-152-13/+34
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Adding FF control set reservationgatecat2021-05-153-58/+148
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Carry fixesgatecat2021-05-152-3/+16
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Carry debugginggatecat2021-05-153-41/+11
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Write arith mode to bitstream (not yet functional)gatecat2021-05-152-2/+18
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: First pass at carry packinggatecat2021-05-154-8/+82
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: FF validity checking fixesgatecat2021-05-151-7/+13
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Fix constant trimminggatecat2021-05-152-1/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Write LUT initsgatecat2021-05-152-1/+72
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add some IO configurationgatecat2021-05-151-0/+30
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Setting some more boilerplate bitsgatecat2021-05-153-1/+118
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add stub RBF generationgatecat2021-05-154-9/+108
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Rename clock buffer primitivegatecat2021-05-152-2/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Python and GUI stubgatecat2021-05-156-0/+350
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Implement some misc. thingsgatecat2021-05-154-10/+78
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Some preps for generating bitstreamsgatecat2021-05-154-28/+131
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Adding a function for computing ALM LUT masksgatecat2021-05-152-0/+90
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add IO packinggatecat2021-05-155-8/+135
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add a basic QSF parsergatecat2021-05-154-1/+295
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add some packing logic based on nexusgatecat2021-05-154-3/+202
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Working on FF validity checkinggatecat2021-05-152-1/+117
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add the 'pin style' stuff based on Nexusgatecat2021-05-152-0/+112
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Working on ALM input assignmentgatecat2021-05-152-2/+118
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add stub pack/place/route functionsgatecat2021-05-155-5/+143
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Renamed arch from cyclonevgatecat2021-05-159-4/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: Rebase updategatecat2021-05-151-1/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: More validity checking thoughtsgatecat2021-05-155-7/+49
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: Add validity check and IO belsgatecat2021-05-155-9/+92
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: First (untested) pass at ALM validity checkinggatecat2021-05-152-40/+135
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: More preparations for validity checkinggatecat2021-05-155-7/+159
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: Preparations for validity checkinggatecat2021-05-152-0/+37
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: Fix some archcheck failsgatecat2021-05-153-4/+6
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
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