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authorgatecat <gatecat@ds0.me>2021-05-08 19:28:11 +0100
committergatecat <gatecat@ds0.me>2021-05-15 14:54:33 +0100
commit1b729d90d0cd7c175da0162e1ba4f0aa6ef48ff0 (patch)
treef8644c063f2ed922c02f47efbb2f9156094f7b28
parentd38ff142644479d9760d32f17bec291e96ab100c (diff)
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mistral: Add the 'pin style' stuff based on Nexus
Signed-off-by: gatecat <gatecat@ds0.me>
-rw-r--r--mistral/arch.h45
-rw-r--r--mistral/pins.cc67
2 files changed, 112 insertions, 0 deletions
diff --git a/mistral/arch.h b/mistral/arch.h
index 3d939c0d..d4f6bd5e 100644
--- a/mistral/arch.h
+++ b/mistral/arch.h
@@ -225,6 +225,45 @@ struct ArchRanges : BaseArchRanges
using AllPipsRangeT = AllPipRange;
};
+// This enum captures different 'styles' of cell pins
+// This is a combination of the modes available for a pin (tied high, low or inverted)
+// and the default value to set it to not connected
+enum CellPinStyle
+{
+ PINOPT_NONE = 0x0, // no options, just signal as-is
+ PINOPT_LO = 0x1, // can be tied low
+ PINOPT_HI = 0x2, // can be tied high
+ PINOPT_INV = 0x4, // can be inverted
+
+ PINOPT_LOHI = 0x3, // can be tied low or high
+ PINOPT_LOHIINV = 0x7, // can be tied low or high; or inverted
+
+ PINOPT_MASK = 0x7,
+
+ PINDEF_NONE = 0x00, // leave disconnected
+ PINDEF_0 = 0x10, // connect to 0 if not used
+ PINDEF_1 = 0x20, // connect to 1 if not used
+
+ PINDEF_MASK = 0x30,
+
+ PINGLB_CLK = 0x100, // pin is a 'clock' for global purposes
+
+ PINGLB_MASK = 0x100,
+
+ PINSTYLE_NONE = 0x000, // default
+
+ PINSTYLE_COMB = 0x017, // combinational signal, defaults low, can be inverted and tied
+ PINSTYLE_CLK = 0x107, // CLK type signal, invertible and defaults to disconnected
+ PINSTYLE_CE = 0x027, // CE type signal, invertible and defaults to enabled
+ PINSTYLE_RST = 0x017, // RST type signal, invertible and defaults to not reset
+ PINSTYLE_DEDI = 0x000, // dedicated signals, leave alone
+ PINSTYLE_INP = 0x001, // general inputs, no inversion/tieing but defaults low
+ PINSTYLE_PU = 0x022, // signals that float high and default high
+
+ PINSTYLE_CARRY = 0x001, // carry chains can be floating or 0?
+
+};
+
struct Arch : BaseArch<ArchRanges>
{
ArchArgs args;
@@ -410,6 +449,12 @@ struct Arch : BaseArch<ArchRanges>
void assign_default_pinmap(CellInfo *cell);
static const std::unordered_map<IdString, IdString> comb_pinmap;
+
+ // -------------------------------------------------
+
+ typedef std::unordered_map<IdString, CellPinStyle> CellPinsData; // pins.cc
+ static const std::unordered_map<IdString, CellPinsData> cell_pins_db; // pins.cc
+ CellPinStyle get_cell_pin_style(const CellInfo *cell, IdString port) const; // pins.cc
};
NEXTPNR_NAMESPACE_END
diff --git a/mistral/pins.cc b/mistral/pins.cc
new file mode 100644
index 00000000..d0ce642e
--- /dev/null
+++ b/mistral/pins.cc
@@ -0,0 +1,67 @@
+/*
+ * nextpnr -- Next Generation Place and Route
+ *
+ * Copyright (C) 2021 gatecat <gatecat@ds0.me>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "log.h"
+#include "nextpnr.h"
+#include "util.h"
+
+NEXTPNR_NAMESPACE_BEGIN
+
+const std::unordered_map<IdString, Arch::CellPinsData> Arch::cell_pins_db = {
+ // For combinational cells, inversion and tieing can be implemented by manipulating the LUT function
+ {id_MISTRAL_ALUT2, {{{}, PINSTYLE_COMB}}},
+ {id_MISTRAL_ALUT3, {{{}, PINSTYLE_COMB}}},
+ {id_MISTRAL_ALUT4, {{{}, PINSTYLE_COMB}}},
+ {id_MISTRAL_ALUT5, {{{}, PINSTYLE_COMB}}},
+ {id_MISTRAL_ALUT6, {{{}, PINSTYLE_COMB}}},
+ {id_MISTRAL_ALUT_ARITH,
+ {// Leave carry chain alone, other than disconnecting a ground constant
+ {id_CI, PINSTYLE_CARRY},
+ {{}, PINSTYLE_COMB}}},
+ {id_MISTRAL_FF,
+ {
+ {id_CLK, PINSTYLE_CLK},
+ {id_ENA, PINSTYLE_CE},
+ {id_ACLR, PINSTYLE_RST},
+ {id_SCLR, PINSTYLE_RST},
+ {id_SLOAD, PINSTYLE_RST},
+ {id_SDATA, PINSTYLE_DEDI},
+ {id_DATAIN, PINSTYLE_INP},
+ }},
+};
+
+CellPinStyle Arch::get_cell_pin_style(const CellInfo *cell, IdString port) const
+{
+ // Look up the pin style in the cell database
+ auto fnd_cell = cell_pins_db.find(cell->type);
+ if (fnd_cell == cell_pins_db.end())
+ return PINSTYLE_NONE;
+ auto fnd_port = fnd_cell->second.find(port);
+ if (fnd_port != fnd_cell->second.end())
+ return fnd_port->second;
+ // If there isn't an exact port match, then the empty IdString
+ // represents a wildcard default match
+ auto fnd_default = fnd_cell->second.find({});
+ if (fnd_default != fnd_cell->second.end())
+ return fnd_default->second;
+
+ return PINSTYLE_NONE;
+}
+
+NEXTPNR_NAMESPACE_END \ No newline at end of file